[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.119 -> 1.120
X86InstrSSE.td updated: 1.16 -> 1.17
---
Log message:

- Supposely movlhps is faster / better than unpcklpd.
- Don't forget pshufd is only available with sse2.


---
Diffs of the changes:  (+16 -11)

 X86ISelLowering.cpp |    5 +++--
 X86InstrSSE.td      |   22 +++++++++++++---------
 2 files changed, 16 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.119 llvm/lib/Target/X86/X86ISelLowering.cpp:1.120
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.119	Wed Mar 22 12:59:22 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Wed Mar 22 13:16:21 2006
@@ -2242,7 +2242,7 @@
         return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1,
                            DAG.getNode(ISD::UNDEF, V1.getValueType()),
                            PermMask);
-    } else if (X86::isPSHUFDMask(PermMask.Val)) {
+    } else if (Subtarget->hasSSE2() && X86::isPSHUFDMask(PermMask.Val)) {
       if (V2.getOpcode() == ISD::UNDEF)
         // Leave the VECTOR_SHUFFLE alone. It matches PSHUFD.
         return SDOperand();
@@ -2375,5 +2375,6 @@
 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
 /// are assumed to be legal.
 bool X86TargetLowering::isShuffleMaskLegal(SDOperand Mask) const {
-  return (X86::isSplatMask(Mask.Val) || X86::isPSHUFDMask(Mask.Val));
+  return (X86::isSplatMask(Mask.Val) ||
+          (Subtarget->hasSSE2() && X86::isPSHUFDMask(Mask.Val)));
 }


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.16 llvm/lib/Target/X86/X86InstrSSE.td:1.17
--- llvm/lib/Target/X86/X86InstrSSE.td:1.16	Wed Mar 22 12:59:22 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Wed Mar 22 13:16:21 2006
@@ -55,7 +55,7 @@
   return X86::isSplatMask(N);
 }], SHUFFLE_get_shuf_imm>;
 
-def UNPCKLP_splat_mask : PatLeaf<(build_vector), [{
+def MOVLHPS_splat_mask : PatLeaf<(build_vector), [{
   return X86::isSplatMask(N);
 }]>;
 
@@ -810,18 +810,22 @@
 
 // Splat v4f32 / v4i32
 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
-          (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>;
+          (v4f32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>,
+  Requires<[HasSSE1]>;
 def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), SHUFP_splat_mask:$sm),
-          (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>;
+          (v4i32 (SHUFPSrr VR128:$src, VR128:$src, SHUFP_splat_mask:$sm))>,
+  Requires<[HasSSE1]>;
 
 // Splat v2f64 / v2i64
-def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), UNPCKLP_splat_mask:$sm),
-          (v2f64 (UNPCKLPDrr VR128:$src, VR128:$src))>;
-def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), UNPCKLP_splat_mask:$sm),
-          (v2i64 (UNPCKLPDrr VR128:$src, VR128:$src))>;
+def : Pat<(vector_shuffle (v2f64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
+          (v2f64 (MOVLHPSrr VR128:$src))>, Requires<[HasSSE1]>;
+def : Pat<(vector_shuffle (v2i64 VR128:$src), (undef), MOVLHPS_splat_mask:$sm),
+          (v2i64 (MOVLHPSrr VR128:$src))>, Requires<[HasSSE1]>;
 
 // Shuffle v4f32 / v4i32, undef. These should only match if splat cases do not.
 def : Pat<(vector_shuffle (v4f32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
-          (v4f32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>;
+          (v4f32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
+  Requires<[HasSSE2]>;
 def : Pat<(vector_shuffle (v4i32 VR128:$src), (undef), PSHUFD_shuffle_mask:$sm),
-          (v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>;
+          (v4i32 (PSHUFDrr VR128:$src, PSHUFD_shuffle_mask:$sm))>,
+  Requires<[HasSSE2]>;