[llvm-commits] CVS: llvm/lib/Target/X86/X86InstrMMX.td X86InstrSSE.td

[Evan Cheng]

Changes in directory llvm/lib/Target/X86:

X86InstrMMX.td updated: 1.3 -> 1.4
X86InstrSSE.td updated: 1.9 -> 1.10
---
Log message:

x86 ISD::SCALAR_TO_VECTOR support.


---
Diffs of the changes:  (+54 -0)

 X86InstrMMX.td |   18 ++++++++++++++++++
 X86InstrSSE.td |   36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 54 insertions(+)


Index: llvm/lib/Target/X86/X86InstrMMX.td
diff -u llvm/lib/Target/X86/X86InstrMMX.td:1.3 llvm/lib/Target/X86/X86InstrMMX.td:1.4
--- llvm/lib/Target/X86/X86InstrMMX.td:1.3	Mon Mar 20 00:04:52 2006
+++ llvm/lib/Target/X86/X86InstrMMX.td	Mon Mar 20 18:33:35 2006
@@ -22,6 +22,24 @@
 def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
 def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>,  Requires<[HasMMX]>;
 
+def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src),
+                              "#SCALAR_TO_VECTOR $src",
+                              [(set VR64:$dst,
+                                (v8i8 (scalar_to_vector R8:$src)))]>,
+                            Requires<[HasMMX]>;
+
+def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR64:$dst,
+                                 (v4i16 (scalar_to_vector R16:$src)))]>,
+                             Requires<[HasMMX]>;
+
+def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR64:$dst,
+                                 (v2i32 (scalar_to_vector R32:$src)))]>,
+                             Requires<[HasMMX]>;
+
 // Move Instructions
 def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src),
                  "movd {$src, $dst|$dst, $src}", []>, TB,


Index: llvm/lib/Target/X86/X86InstrSSE.td
diff -u llvm/lib/Target/X86/X86InstrSSE.td:1.9 llvm/lib/Target/X86/X86InstrSSE.td:1.10
--- llvm/lib/Target/X86/X86InstrSSE.td:1.9	Mon Mar 20 00:04:52 2006
+++ llvm/lib/Target/X86/X86InstrSSE.td	Mon Mar 20 18:33:35 2006
@@ -353,6 +353,42 @@
 def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
 def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>;
 
+def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR128:$dst,
+                                 (v4f32 (scalar_to_vector FR32:$src)))]>,
+                             Requires<[HasSSE1]>;
+
+def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR128:$dst,
+                                 (v2f64 (scalar_to_vector FR64:$src)))]>,
+                             Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR128:$dst,
+                                 (v16i8 (scalar_to_vector R8:$src)))]>,
+                             Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR128:$dst,
+                                 (v8i16 (scalar_to_vector R16:$src)))]>,
+                             Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR128:$dst,
+                                 (v4i32 (scalar_to_vector R32:$src)))]>,
+                             Requires<[HasSSE2]>;
+
+def SCALAR_TO_VECTOR_V2I64 : I<0, Pseudo, (ops VR128:$dst, VR64:$src),
+                               "#SCALAR_TO_VECTOR $src",
+                               [(set VR128:$dst,
+                                 (v2i64 (scalar_to_vector VR64:$src)))]>,
+                             Requires<[HasSSE2]>;
+
 // Move Instructions
 def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src),
                    "movaps {$src, $dst|$dst, $src}", []>;