[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCInstrInfo.td

[Evan Cheng]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.170 -> 1.171
PPCInstrInfo.td updated: 1.197 -> 1.198
---
Log message:

Use tblgen'd VECTOR_SHUFFLE selection code.

---
Diffs of the changes:  (+2 -19)

 PPCISelDAGToDAG.cpp |   16 ----------------
 PPCInstrInfo.td     |    5 ++---
 2 files changed, 2 insertions(+), 19 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.171
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.170	Mon Mar 20 00:51:10 2006
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Mon Mar 20 02:14:16 2006
@@ -927,22 +927,6 @@
   
   switch (N->getOpcode()) {
   default: break;
-  case ISD::VECTOR_SHUFFLE:
-    // FIXME: This should be autogenerated from the .td file, it is here for now
-    // due to bugs in tblgen.
-    if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
-        (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
-        PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
-      SDOperand N0;
-      Select(N0, N->getOperand(0));
-
-      Result = CodeGenMap[Op] = 
-        SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
-                      getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
-                                        N0), 0);
-      return;
-    }
-    assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
   case ISD::SETCC:
     Result = SelectSETCC(Op);
     return;


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.198
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.197	Mon Mar 20 00:51:10 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Mon Mar 20 02:14:16 2006
@@ -1034,9 +1034,8 @@
                       
 def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
                       "vspltw $vD, $vB, $UIMM", VecPerm,
-                      [/*
-                       (set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
-                                      VSPLT_shuffle_mask:$UIMM))*/]>;
+                      [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
+                                      VSPLT_shuffle_mask:$UIMM))]>;
                       // FIXME: ALSO ADD SUPPORT FOR v4i32!
                       
 // VX-Form Pseudo Instructions