[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelLowering.cpp PPCISelLowering.h PPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelLowering.cpp updated: 1.99 -> 1.100
PPCISelLowering.h updated: 1.26 -> 1.27
PPCInstrInfo.td updated: 1.190 -> 1.191
---
Log message:

Custom lower SCALAR_TO_VECTOR into lve*x.


---
Diffs of the changes:  (+37 -9)

 PPCISelLowering.cpp |   20 ++++++++++++++++++--
 PPCISelLowering.h   |    8 ++++++++
 PPCInstrInfo.td     |   18 +++++++++++-------
 3 files changed, 37 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.100
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.99	Sun Mar 19 00:17:19 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Sun Mar 19 00:55:52 2006
@@ -184,8 +184,8 @@
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
     setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
     
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Expand);
-    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Expand);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
+    setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
   }
   
   setSetCCResultContents(ZeroOrOneSetCCResult);
@@ -208,6 +208,7 @@
   case PPCISD::STFIWX:        return "PPCISD::STFIWX";
   case PPCISD::VMADDFP:       return "PPCISD::VMADDFP";
   case PPCISD::VNMSUBFP:      return "PPCISD::VNMSUBFP";
+  case PPCISD::LVE_X:         return "PPCISD::LVE_X";
   case PPCISD::Hi:            return "PPCISD::Hi";
   case PPCISD::Lo:            return "PPCISD::Lo";
   case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
@@ -550,6 +551,21 @@
     }
     return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
   }
+  case ISD::SCALAR_TO_VECTOR: {
+    // Create a stack slot that is 16-byte aligned.
+    MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
+    int FrameIdx = FrameInfo->CreateStackObject(16, 16);
+    SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
+    
+    // Store the input value into Value#0 of the stack slot.
+    unsigned InSize = MVT::getSizeInBits(Op.getOperand(0).getValueType())/8;
+    FIdx = DAG.getNode(ISD::ADD, MVT::i32, FIdx,
+                       DAG.getConstant(16-InSize, MVT::i32));
+    SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
+                                  Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
+    return DAG.getNode(PPCISD::LVE_X, Op.getValueType(), Store, FIdx, 
+                       DAG.getSrcValue(NULL));
+  }
   }
   return SDOperand();
 }


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.27
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.26	Mon Mar 13 17:20:37 2006
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Sun Mar 19 00:55:52 2006
@@ -48,6 +48,14 @@
       // three v4f32 operands and producing a v4f32 result.
       VMADDFP, VNMSUBFP,
       
+      /// LVE_X - The PPC LVE*X instructions.  The size of the element loaded is
+      /// the size of the element type of the vector result.  The element loaded
+      /// depends on the alignment of the input pointer.
+      ///
+      /// The first operand is a token chain, the second is the address to load
+      /// the third is the SRCVALUE node.
+      LVE_X,
+      
       /// Hi/Lo - These represent the high and low 16-bit parts of a global
       /// address respectively.  These nodes have two operands, the first of
       /// which must be a TargetGlobalAddress, and the second of which must be a


Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190 llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.191
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td:1.190	Sun Mar 19 00:10:09 2006
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td	Sun Mar 19 00:55:52 2006
@@ -45,6 +45,8 @@
 def PPCvmaddfp  : SDNode<"PPCISD::VMADDFP", SDTFPTernaryOp, []>;
 def PPCvnmsubfp : SDNode<"PPCISD::VNMSUBFP", SDTFPTernaryOp, []>;
 
+def PPClve_x    : SDNode<"PPCISD::LVE_X", SDTLoad, [SDNPHasChain]>;
+
 // These nodes represent the 32-bit PPC shifts that operate on 6-bit shift
 // amounts.  These nodes are generated by the multi-precision shift code.
 def PPCsrl        : SDNode<"PPCISD::SRL"       , SDT_PPCShiftOp>;
@@ -451,15 +453,15 @@
 def LDX  : XForm_1<31,  21, (ops G8RC:$rD, memrr:$src),
                    "ldx $rD, $src", LdStLD,
                    [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
-def LVEBX: XForm_1<31,   7, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvebx $vD, $base, $rA", LdStGeneral,
-                   []>;
-def LVEHX: XForm_1<31,  39, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvehx $vD, $base, $rA", LdStGeneral,
+def LVEBX: XForm_1<31,   7, (ops VRRC:$vD, memrr:$src),
+                   "lvebx $vD, $src", LdStGeneral,
                    []>;
-def LVEWX: XForm_1<31,  71, (ops VRRC:$vD,  GPRC:$base, GPRC:$rA),
-                   "lvewx $vD, $base, $rA", LdStGeneral,
+def LVEHX: XForm_1<31,  39, (ops VRRC:$vD,  memrr:$src),
+                   "lvehx $vD, $src", LdStGeneral,
                    []>;
+def LVEWX: XForm_1<31,  71, (ops VRRC:$vD,  memrr:$src),
+                   "lvewx $vD, $src", LdStGeneral,
+                   [(set VRRC:$vD, (v4f32 (PPClve_x xoaddr:$src)))]>;
 def LVX  : XForm_1<31, 103, (ops VRRC:$vD,  memrr:$src),
                    "lvx $vD, $src", LdStGeneral,
                    [(set VRRC:$vD, (v4f32 (load xoaddr:$src)))]>;
@@ -1149,6 +1151,8 @@
           (v4i32 (LVX xoaddr:$src))>;
 def : Pat<(store (v4i32 VRRC:$rS), xoaddr:$dst),
           (STVX (v4i32 VRRC:$rS), xoaddr:$dst)>;
+def : Pat<(v4i32 (PPClve_x xoaddr:$src)),
+          (v4i32 (LVEWX xoaddr:$src))>;
 
 def : Pat<(v4i32 (undef)), (v4i32 (IMPLICIT_DEF_VRRC))>;