[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.111 -> 1.112
---
Log message:

rename these nodes


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Diffs of the changes:  (+9 -9)

 X86ISelLowering.cpp |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.111 llvm/lib/Target/X86/X86ISelLowering.cpp:1.112
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.111	Fri Mar 17 14:31:41 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Sat Mar 18 19:13:28 2006
@@ -263,9 +263,9 @@
     addRegisterClass(MVT::v2i32, X86::VR64RegisterClass);
 
     // FIXME: add MMX packed arithmetics
-    setOperationAction(ISD::ConstantVec, MVT::v8i8,  Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v4i16, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v2i32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8,  Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Expand);
   }
 
   if (TM.getSubtarget<X86Subtarget>().hasSSE1()) {
@@ -275,7 +275,7 @@
     setOperationAction(ISD::SUB        , MVT::v4f32, Legal);
     setOperationAction(ISD::MUL        , MVT::v4f32, Legal);
     setOperationAction(ISD::LOAD       , MVT::v4f32, Legal);
-    setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Expand);
   }
 
   if (TM.getSubtarget<X86Subtarget>().hasSSE2()) {
@@ -290,11 +290,11 @@
     setOperationAction(ISD::SUB        , MVT::v2f64, Legal);
     setOperationAction(ISD::MUL        , MVT::v2f64, Legal);
     setOperationAction(ISD::LOAD       , MVT::v2f64, Legal);
-    setOperationAction(ISD::ConstantVec, MVT::v2f64, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v16i8, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v8i16, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
-    setOperationAction(ISD::ConstantVec, MVT::v2i64, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Expand);
+    setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Expand);
   }
 
   computeRegisterProperties();