[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPCHazardRecognizers.cpp updated: 1.2 -> 1.3
---
Log message:

add some new instructions to the classifier.  With this, we correctly insert
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).


---
Diffs of the changes:  (+11 -0)

 PPCHazardRecognizers.cpp |   11 +++++++++++
 1 files changed, 11 insertions(+)


Index: llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
diff -u llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.2 llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.3
--- llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp:1.2	Tue Mar  7 00:44:19 2006
+++ llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp	Tue Mar  7 01:14:55 2006
@@ -41,6 +41,7 @@
 // conditions, we insert no-op instructions when appropriate.
 //
 // FIXME: This is missing some significant cases:
+//  -1. Handle all of the instruction types in GetInstrType.
 //   0. Handling of instructions that must be the first/last in a group.
 //   1. Modeling of microcoded instructions.
 //   2. Handling of cracked instructions.
@@ -76,12 +77,18 @@
   case PPC::BLA:
     return BR;
   case PPC::LFS:
+  case PPC::LFD:
   case PPC::LWZ:
+  case PPC::LFSX:
+  case PPC::LWZX:
     return LSU_LD;
   case PPC::STFD:
+  case PPC::STW:
     return LSU_ST;
   case PPC::FADDS:
   case PPC::FCTIWZ:
+  case PPC::FRSP:
+  case PPC::FSUB:
     return FPU;
   }
   
@@ -159,8 +166,11 @@
     unsigned LoadSize;
     switch (Opcode) {
     default: assert(0 && "Unknown load!");
+    case PPC::LFSX:
     case PPC::LFS:
+    case PPC::LWZX:
     case PPC::LWZ: LoadSize = 4; break;
+    case PPC::LFD: LoadSize = 8; break;
     }
     
     if (isLoadOfStoredAddress(LoadSize, 
@@ -186,6 +196,7 @@
     switch (Opcode) {
     default: assert(0 && "Unknown store instruction!");
     case PPC::STFD: StoreSize = 8; break;
+    case PPC::STW:  StoreSize = 4; break;
     }
   }