[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.308 -> 1.309
SelectionDAG.cpp updated: 1.262 -> 1.263
SelectionDAGISel.cpp updated: 1.176 -> 1.177
---
Log message:

remove the read/write port/io intrinsics.


---
Diffs of the changes:  (+0 -91)

 LegalizeDAG.cpp      |   62 ---------------------------------------------------
 SelectionDAG.cpp     |    6 ----
 SelectionDAGISel.cpp |   23 ------------------
 3 files changed, 91 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.308 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.309
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.308	Tue Feb 28 19:09:54 2006
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Mar  2 18:19:44 2006
@@ -1691,68 +1691,6 @@
     break;
   }
 
-  case ISD::READPORT:
-    Tmp1 = LegalizeOp(Node->getOperand(0));
-    Tmp2 = LegalizeOp(Node->getOperand(1));
-    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
-
-    // Since these produce two values, make sure to remember that we legalized
-    // both of them.
-    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
-    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
-    return Result;
-  case ISD::WRITEPORT:
-    Tmp1 = LegalizeOp(Node->getOperand(0));
-    Tmp2 = LegalizeOp(Node->getOperand(1));
-    Tmp3 = LegalizeOp(Node->getOperand(2));
-    Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-    break;
-
-  case ISD::READIO:
-    Tmp1 = LegalizeOp(Node->getOperand(0));
-    Tmp2 = LegalizeOp(Node->getOperand(1));
-
-    switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
-    case TargetLowering::Custom:
-    default: assert(0 && "This action not implemented for this operation!");
-    case TargetLowering::Legal:
-      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2);
-      break;
-    case TargetLowering::Expand:
-      // Replace this with a load from memory.
-      Result = DAG.getLoad(Node->getValueType(0), Node->getOperand(0),
-                           Node->getOperand(1), DAG.getSrcValue(NULL));
-      Result = LegalizeOp(Result);
-      break;
-    }
-
-    // Since these produce two values, make sure to remember that we legalized
-    // both of them.
-    AddLegalizedOperand(SDOperand(Node, 0), Result.getValue(0));
-    AddLegalizedOperand(SDOperand(Node, 1), Result.getValue(1));
-    return Result.getValue(Op.ResNo);
-
-  case ISD::WRITEIO:
-    Tmp1 = LegalizeOp(Node->getOperand(0));
-    Tmp2 = LegalizeOp(Node->getOperand(1));
-    Tmp3 = LegalizeOp(Node->getOperand(2));
-
-    switch (TLI.getOperationAction(Node->getOpcode(),
-                                   Node->getOperand(1).getValueType())) {
-    case TargetLowering::Custom:
-    default: assert(0 && "This action not implemented for this operation!");
-    case TargetLowering::Legal:
-      Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, Tmp3);
-      break;
-    case TargetLowering::Expand:
-      // Replace this with a store to memory.
-      Result = DAG.getNode(ISD::STORE, MVT::Other, Node->getOperand(0),
-                           Node->getOperand(1), Node->getOperand(2),
-                           DAG.getSrcValue(NULL));
-      break;
-    }
-    break;
-
   case ISD::SHL_PARTS:
   case ISD::SRA_PARTS:
   case ISD::SRL_PARTS: {


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.262 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.263
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.262	Tue Feb 28 18:51:13 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Mar  2 18:19:44 2006
@@ -2691,12 +2691,6 @@
   case ISD::CTTZ:    return "cttz";
   case ISD::CTLZ:    return "ctlz";
 
-  // IO Intrinsics
-  case ISD::READPORT: return "readport";
-  case ISD::WRITEPORT: return "writeport";
-  case ISD::READIO: return "readio";
-  case ISD::WRITEIO: return "writeio";
-
   // Debug info
   case ISD::LOCATION: return "location";
   case ISD::DEBUG_LOC: return "debug_loc";


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.176 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.177
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.176	Thu Mar  2 18:00:25 2006
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Thu Mar  2 18:19:44 2006
@@ -968,29 +968,6 @@
     visitMemIntrinsic(I, ISD::MEMMOVE);
     return 0;
     
-  case Intrinsic::readport:
-  case Intrinsic::readio: {
-    std::vector<MVT::ValueType> VTs;
-    VTs.push_back(TLI.getValueType(I.getType()));
-    VTs.push_back(MVT::Other);
-    std::vector<SDOperand> Ops;
-    Ops.push_back(getRoot());
-    Ops.push_back(getValue(I.getOperand(1)));
-    SDOperand Tmp = DAG.getNode(Intrinsic == Intrinsic::readport ?
-                                ISD::READPORT : ISD::READIO, VTs, Ops);
-    
-    setValue(&I, Tmp);
-    DAG.setRoot(Tmp.getValue(1));
-    return 0;
-  }
-  case Intrinsic::writeport:
-  case Intrinsic::writeio:
-    DAG.setRoot(DAG.getNode(Intrinsic == Intrinsic::writeport ?
-                            ISD::WRITEPORT : ISD::WRITEIO, MVT::Other,
-                            getRoot(), getValue(I.getOperand(1)),
-                            getValue(I.getOperand(2))));
-    return 0;
-    
   case Intrinsic::dbg_stoppoint: {
     if (TLI.getTargetMachine().getIntrinsicLowering().EmitDebugFunctions())
       return "llvm_debugger_stop";