[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelLowering.cpp X86ISelLowering.h

[Nate Begeman]

Changes in directory llvm/lib/Target/X86:

X86ISelLowering.cpp updated: 1.83 -> 1.84
X86ISelLowering.h updated: 1.25 -> 1.26
---
Log message:

Rework the SelectionDAG-based implementations of SimplifyDemandedBits
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.


---
Diffs of the changes:  (+18 -11)

 X86ISelLowering.cpp |   14 +++++++++-----
 X86ISelLowering.h   |   15 +++++++++------
 2 files changed, 18 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/X86/X86ISelLowering.cpp
diff -u llvm/lib/Target/X86/X86ISelLowering.cpp:1.83 llvm/lib/Target/X86/X86ISelLowering.cpp:1.84
--- llvm/lib/Target/X86/X86ISelLowering.cpp:1.83	Wed Feb 15 18:21:07 2006
+++ llvm/lib/Target/X86/X86ISelLowering.cpp	Thu Feb 16 15:11:51 2006
@@ -2035,19 +2035,23 @@
   }
 }
 
-bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
-                                                       uint64_t Mask) const {
+void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
+                                                       uint64_t Mask,
+                                                       uint64_t &KnownZero, 
+                                                       uint64_t &KnownOne,
+                                                       unsigned Depth) const {
 
   unsigned Opc = Op.getOpcode();
+  KnownZero = KnownOne = 0;   // Don't know anything.
 
   switch (Opc) {
   default:
     assert(Opc >= ISD::BUILTIN_OP_END && "Expected a target specific node");
     break;
-  case X86ISD::SETCC: return (Mask & 1) == 0;
+  case X86ISD::SETCC: 
+    KnownZero |= (MVT::getIntVTBitMask(Op.getValueType()) ^ 1ULL);
+    break;
   }
-
-  return false;
 }
 
 std::vector<unsigned> X86TargetLowering::


Index: llvm/lib/Target/X86/X86ISelLowering.h
diff -u llvm/lib/Target/X86/X86ISelLowering.h:1.25 llvm/lib/Target/X86/X86ISelLowering.h:1.26
--- llvm/lib/Target/X86/X86ISelLowering.h:1.25	Fri Feb  3 20:20:30 2006
+++ llvm/lib/Target/X86/X86ISelLowering.h	Thu Feb 16 15:11:51 2006
@@ -218,12 +218,15 @@
     /// DAG node.
     virtual const char *getTargetNodeName(unsigned Opcode) const;
 
-    /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
-    /// be zero. Op is expected to be a target specific node. Used by DAG
-    /// combiner.
-    virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op,
-                                                uint64_t Mask) const;
-
+    /// computeMaskedBitsForTargetNode - Determine which of the bits specified 
+    /// in Mask are known to be either zero or one and return them in the 
+    /// KnownZero/KnownOne bitsets.
+    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
+                                                uint64_t Mask,
+                                                uint64_t &KnownZero, 
+                                                uint64_t &KnownOne,
+                                                unsigned Depth = 0) const;
+    
     SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
 
     std::vector<unsigned>