[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp AlphaInstrFormats.td

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelDAGToDAG.cpp updated: 1.27 -> 1.28
AlphaISelLowering.cpp updated: 1.22 -> 1.23
AlphaInstrFormats.td updated: 1.22 -> 1.23
---
Log message:

stack and rpcc

---
Diffs of the changes:  (+11 -35)

 AlphaISelDAGToDAG.cpp |   36 +++++-------------------------------
 AlphaISelLowering.cpp |    5 ++++-
 AlphaInstrFormats.td  |    5 ++---
 3 files changed, 11 insertions(+), 35 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.27 llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.28
--- llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp:1.27	Fri Jan  6 13:41:51 2006
+++ llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp	Mon Jan 16 15:22:38 2006
@@ -163,37 +163,6 @@
   case ISD::TAILCALL:
   case ISD::CALL: return SelectCALL(Op);
 
-  case ISD::DYNAMIC_STACKALLOC: {
-    if (!isa<ConstantSDNode>(N->getOperand(2)) ||
-        cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) {
-      std::cerr << "Cannot allocate stack object with greater alignment than"
-                << " the stack alignment yet!";
-      abort();
-    }
-
-    SDOperand Chain = Select(N->getOperand(0));
-    SDOperand Amt   = Select(N->getOperand(1));
-    SDOperand Reg = CurDAG->getRegister(Alpha::R30, MVT::i64);
-    SDOperand Val = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
-    Chain = Val.getValue(1);
-    
-    // Subtract the amount (guaranteed to be a multiple of the stack alignment)
-    // from the stack pointer, giving us the result pointer.
-    SDOperand Result = CurDAG->getTargetNode(Alpha::SUBQ, MVT::i64, Val, Amt);
-    
-    // Copy this result back into R30.
-    Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, Result);
-    
-    // Copy this result back out of R30 to make sure we're not using the stack
-    // space without decrementing the stack pointer.
-    Result = CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64);
-  
-    // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg.
-    CodeGenMap[Op.getValue(0)] = Result;
-    CodeGenMap[Op.getValue(1)] = Result.getValue(1);
-    return SDOperand(Result.Val, Op.ResNo);
-  }
-
   case ISD::FrameIndex: {
     int FI = cast<FrameIndexSDNode>(N)->getIndex();
     return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
@@ -218,6 +187,11 @@
     return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
   }
 
+  case ISD::READCYCLECOUNTER: {
+    SDOperand Chain = Select(N->getOperand(0)); //Select chain
+    return CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
+  }
+
   case ISD::RET: {
     SDOperand Chain = Select(N->getOperand(0));     // Token chain.
     SDOperand InFlag;


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.22 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.23
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.22	Mon Jan 16 13:53:25 2006
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Mon Jan 16 15:22:38 2006
@@ -112,7 +112,8 @@
   // Not implemented yet.
   setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 
   setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
-  
+  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
+
   // We want to legalize GlobalAddress and ConstantPool and
   // ExternalSymbols nodes into the appropriate instructions to
   // materialize the address.
@@ -120,6 +121,8 @@
   setOperationAction(ISD::ConstantPool,   MVT::i64, Custom);
   setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
 
+  setStackPointerRegisterToSaveRestore(Alpha::R30);
+
   addLegalFPImmediate(+0.0); //F31
   addLegalFPImmediate(-0.0); //-F31
 


Index: llvm/lib/Target/Alpha/AlphaInstrFormats.td
diff -u llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.22 llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.23
--- llvm/lib/Target/Alpha/AlphaInstrFormats.td:1.22	Sun Jan  1 16:16:14 2006
+++ llvm/lib/Target/Alpha/AlphaInstrFormats.td	Mon Jan 16 15:22:38 2006
@@ -65,12 +65,11 @@
   let Inst{15-0} = disp;
 }
 class MfcForm<bits<6> opcode, bits<16> fc, string asmstr> 
-        : InstAlpha<opcode, (ops GPRC:$RA, GPRC:$RB), asmstr> {
+        : InstAlpha<opcode, (ops GPRC:$RA), asmstr> {
   bits<5> Ra;
-  bits<5> Rb;
 
   let Inst{25-21} = Ra;
-  let Inst{20-16} = Rb;
+  let Inst{20-16} = 0;
   let Inst{15-0} = fc;
 }