[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.81 -> 1.82
---
Log message:

Add a simple missing fold to produce this:

        subfic r3, r2, 33

instead of this:

        subfic r2, r2, 32
        addi r3, r2, 1



---
Diffs of the changes:  (+8 -0)

 DAGCombiner.cpp |    8 ++++++++
 1 files changed, 8 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.81 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.82
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.81	Thu Jan 12 12:57:33 2006
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Thu Jan 12 14:22:43 2006
@@ -696,6 +696,14 @@
       return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
                          DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
   }
+  
+  // fold ((c1-A)+c2) -> (c1+c2)-A
+  if (N1C && N0.getOpcode() == ISD::SUB)
+    if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0)))
+      return DAG.getNode(ISD::SUB, VT,
+                         DAG.getConstant(N1C->getValue()+N0C->getValue(), VT),
+                         N0.getOperand(1));
+  
   // fold ((0-A) + B) -> B-A
   if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
       cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())