[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelLowering.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/IA64:

IA64ISelLowering.cpp updated: 1.16 -> 1.17
---
Log message:

Fix an itanium call lowering bug for duraid


---
Diffs of the changes:  (+6 -6)

 IA64ISelLowering.cpp |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelLowering.cpp
diff -u llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.16 llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.17
--- llvm/lib/Target/IA64/IA64ISelLowering.cpp:1.16	Wed Jan 11 15:21:00 2006
+++ llvm/lib/Target/IA64/IA64ISelLowering.cpp	Wed Jan 11 19:33:08 2006
@@ -376,14 +376,14 @@
   
   // save the current GP, SP and RP : FIXME: do we need to do all 3 always?
   SDOperand GPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r1, MVT::i64, InFlag);
-  Chain = GPBeforeCall;
-  InFlag = Chain.getValue(1);
+  Chain = GPBeforeCall.getValue(1);
+  InFlag = Chain.getValue(2);
   SDOperand SPBeforeCall = DAG.getCopyFromReg(Chain, IA64::r12, MVT::i64, InFlag);
-  Chain = SPBeforeCall;
-  InFlag = Chain.getValue(1);
+  Chain = SPBeforeCall.getValue(1);
+  InFlag = Chain.getValue(2);
   SDOperand RPBeforeCall = DAG.getCopyFromReg(Chain, IA64::rp, MVT::i64, InFlag);
-  Chain = RPBeforeCall;
-  InFlag = Chain.getValue(1);
+  Chain = RPBeforeCall.getValue(1);
+  InFlag = Chain.getValue(2);
 
   // Build a sequence of copy-to-reg nodes chained together with token chain
   // and flag operands which copy the outgoing integer args into regs out[0-7]