[llvm-commits] CVS: llvm/lib/Target/X86/X86FloatingPoint.cpp X86InstrInfo.td

Evan Cheng evan.cheng at apple.com
Tue Jan 10 14:22:15 PST 2006



Changes in directory llvm/lib/Target/X86:

X86FloatingPoint.cpp updated: 1.45 -> 1.46
X86InstrInfo.td updated: 1.193 -> 1.194
---
Log message:

* fp to sint patterns.
* fiadd, fisub, etc.


---
Diffs of the changes:  (+119 -56)

 X86FloatingPoint.cpp |   92 ++++++++++++++++++++++++++++-----------------------
 X86InstrInfo.td      |   83 +++++++++++++++++++++++++++++++++++++---------
 2 files changed, 119 insertions(+), 56 deletions(-)


Index: llvm/lib/Target/X86/X86FloatingPoint.cpp
diff -u llvm/lib/Target/X86/X86FloatingPoint.cpp:1.45 llvm/lib/Target/X86/X86FloatingPoint.cpp:1.46
--- llvm/lib/Target/X86/X86FloatingPoint.cpp:1.45	Wed Dec 21 01:47:04 2005
+++ llvm/lib/Target/X86/X86FloatingPoint.cpp	Tue Jan 10 16:22:02 2006
@@ -320,46 +320,58 @@
 // concrete X86 instruction which uses the register stack.
 //
 static const TableEntry OpcodeTable[] = {
-  { X86::FpABS    , X86::FABS     },
-  { X86::FpADD32m , X86::FADD32m  },
-  { X86::FpADD64m , X86::FADD64m  },
-  { X86::FpCHS    , X86::FCHS     },
-  { X86::FpCMOVA  , X86::FCMOVA   },
-  { X86::FpCMOVAE , X86::FCMOVAE  },
-  { X86::FpCMOVB  , X86::FCMOVB   },
-  { X86::FpCMOVBE , X86::FCMOVBE  },
-  { X86::FpCMOVE  , X86::FCMOVE   },
-  { X86::FpCMOVNE , X86::FCMOVNE  },
-  { X86::FpCMOVNP , X86::FCMOVNP  },
-  { X86::FpCMOVP  , X86::FCMOVP   },
-  { X86::FpCOS    , X86::FCOS     },
-  { X86::FpDIV32m , X86::FDIV32m  },
-  { X86::FpDIV64m , X86::FDIV64m  },
-  { X86::FpDIVR32m, X86::FDIVR32m },
-  { X86::FpDIVR64m, X86::FDIVR64m },
-  { X86::FpILD16m , X86::FILD16m  },
-  { X86::FpILD32m , X86::FILD32m  },
-  { X86::FpILD64m , X86::FILD64m  },
-  { X86::FpIST16m , X86::FIST16m  },
-  { X86::FpIST32m , X86::FIST32m  },
-  { X86::FpIST64m , X86::FISTP64m },
-  { X86::FpLD0    , X86::FLD0     },
-  { X86::FpLD1    , X86::FLD1     },
-  { X86::FpLD32m  , X86::FLD32m   },
-  { X86::FpLD64m  , X86::FLD64m   },
-  { X86::FpMUL32m , X86::FMUL32m  },
-  { X86::FpMUL64m , X86::FMUL64m  },
-  { X86::FpSIN    , X86::FSIN     },
-  { X86::FpSQRT   , X86::FSQRT    },
-  { X86::FpST32m  , X86::FST32m   },
-  { X86::FpST64m  , X86::FST64m   },
-  { X86::FpSUB32m , X86::FSUB32m  },
-  { X86::FpSUB64m , X86::FSUB64m  },
-  { X86::FpSUBR32m, X86::FSUBR32m },
-  { X86::FpSUBR64m, X86::FSUBR64m },
-  { X86::FpTST    , X86::FTST     },
-  { X86::FpUCOMIr , X86::FUCOMIr  },
-  { X86::FpUCOMr  , X86::FUCOMr   },
+  { X86::FpABS     , X86::FABS     },
+  { X86::FpADD32m  , X86::FADD32m  },
+  { X86::FpADD64m  , X86::FADD64m  },
+  { X86::FpCHS     , X86::FCHS     },
+  { X86::FpCMOVA   , X86::FCMOVA   },
+  { X86::FpCMOVAE  , X86::FCMOVAE  },
+  { X86::FpCMOVB   , X86::FCMOVB   },
+  { X86::FpCMOVBE  , X86::FCMOVBE  },
+  { X86::FpCMOVE   , X86::FCMOVE   },
+  { X86::FpCMOVNE  , X86::FCMOVNE  },
+  { X86::FpCMOVNP  , X86::FCMOVNP  },
+  { X86::FpCMOVP   , X86::FCMOVP   },
+  { X86::FpCOS     , X86::FCOS     },
+  { X86::FpDIV32m  , X86::FDIV32m  },
+  { X86::FpDIV64m  , X86::FDIV64m  },
+  { X86::FpDIVR32m , X86::FDIVR32m },
+  { X86::FpDIVR64m , X86::FDIVR64m },
+  { X86::FpIADD16m , X86::FIADD16m },
+  { X86::FpIADD32m , X86::FIADD32m },
+  { X86::FpIDIV16m , X86::FIDIV16m },
+  { X86::FpIDIV32m , X86::FIDIV32m },
+  { X86::FpIDIVR16m, X86::FIDIVR16m},
+  { X86::FpIDIVR32m, X86::FIDIVR32m},
+  { X86::FpILD16m  , X86::FILD16m  },
+  { X86::FpILD32m  , X86::FILD32m  },
+  { X86::FpILD64m  , X86::FILD64m  },
+  { X86::FpIMUL16m , X86::FIMUL16m },
+  { X86::FpIMUL32m , X86::FIMUL32m },
+  { X86::FpIST16m  , X86::FIST16m  },
+  { X86::FpIST32m  , X86::FIST32m  },
+  { X86::FpIST64m  , X86::FISTP64m },
+  { X86::FpISUB16m , X86::FISUB16m },
+  { X86::FpISUB32m , X86::FISUB32m },
+  { X86::FpISUBR16m, X86::FISUBR16m},
+  { X86::FpISUBR32m, X86::FISUBR32m},
+  { X86::FpLD0     , X86::FLD0     },
+  { X86::FpLD1     , X86::FLD1     },
+  { X86::FpLD32m   , X86::FLD32m   },
+  { X86::FpLD64m   , X86::FLD64m   },
+  { X86::FpMUL32m  , X86::FMUL32m  },
+  { X86::FpMUL64m  , X86::FMUL64m  },
+  { X86::FpSIN     , X86::FSIN     },
+  { X86::FpSQRT    , X86::FSQRT    },
+  { X86::FpST32m   , X86::FST32m   },
+  { X86::FpST64m   , X86::FST64m   },
+  { X86::FpSUB32m  , X86::FSUB32m  },
+  { X86::FpSUB64m  , X86::FSUB64m  },
+  { X86::FpSUBR32m , X86::FSUBR32m },
+  { X86::FpSUBR64m , X86::FSUBR64m },
+  { X86::FpTST     , X86::FTST     },
+  { X86::FpUCOMIr  , X86::FUCOMIr  },
+  { X86::FpUCOMr   , X86::FUCOMr   },
 };
 
 static unsigned getConcreteOpcode(unsigned Opcode) {


Index: llvm/lib/Target/X86/X86InstrInfo.td
diff -u llvm/lib/Target/X86/X86InstrInfo.td:1.193 llvm/lib/Target/X86/X86InstrInfo.td:1.194
--- llvm/lib/Target/X86/X86InstrInfo.td:1.193	Tue Jan 10 14:26:56 2006
+++ llvm/lib/Target/X86/X86InstrInfo.td	Tue Jan 10 16:22:02 2006
@@ -50,6 +50,7 @@
                                          SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
 def SDTX86Fst     : SDTypeProfile<0, 3, [SDTCisFP<0>,
                                          SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>]>;
+def SDTX86Fild64m : SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisPtrTy<1>]>;
 
 def SDTX86RdTsc   : SDTypeProfile<0, 0, []>;
 
@@ -95,6 +96,8 @@
                         [SDNPHasChain]>;
 def X86fst     : SDNode<"X86ISD::FST",      SDTX86Fst,
                         [SDNPHasChain]>;
+def X86fild64m : SDNode<"X86ISD::FILD64m",  SDTX86Fild64m,
+                        [SDNPHasChain]>;
 
 def X86rdtsc   : SDNode<"X86ISD::RDTSC_DAG",SDTX86RdTsc,
                         [SDNPHasChain, SDNPOutFlag]>;
@@ -2633,19 +2636,67 @@
 def FDIVR64m : FPI<0xDC, MRM7m, (ops f64mem:$src), "fdivr{l} $src">;
 
 // FIXME: Implement these when we have a dag-dag isel!
-//def FIADD16m  : FPI<0xDE, MRM0m>;    // ST(0) = ST(0) + [mem16int]
-//def FIADD32m  : FPI<0xDA, MRM0m>;    // ST(0) = ST(0) + [mem32int]
-//def FIMUL16m  : FPI<0xDE, MRM1m>;    // ST(0) = ST(0) * [mem16]
-//def FIMUL32m  : FPI<0xDA, MRM1m>;    // ST(0) = ST(0) * [mem32]
-//def FISUB16m  : FPI<0xDE, MRM4m>;    // ST(0) = ST(0) - [mem16int]
-//def FISUB32m  : FPI<0xDA, MRM4m>;    // ST(0) = ST(0) - [mem32int]
-//def FISUBR16m : FPI<0xDE, MRM5m>;    // ST(0) = [mem16int] - ST(0)
-//def FISUBR32m : FPI<0xDA, MRM5m>;    // ST(0) = [mem32int] - ST(0)
-//def FIDIV16m  : FPI<0xDE, MRM6m>;    // ST(0) = ST(0) / [mem16int]
-//def FIDIV32m  : FPI<0xDA, MRM6m>;    // ST(0) = ST(0) / [mem32int]
-//def FIDIVR16m : FPI<0xDE, MRM7m>;    // ST(0) = [mem16int] / ST(0)
-//def FIDIVR32m : FPI<0xDA, MRM7m>;    // ST(0) = [mem32int] / ST(0)
-
+def FpIADD16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fadd RFP:$src1,
+                                     (sint_to_fp (loadi16 addr:$src2))))]>;
+                // ST(0) = ST(0) + [mem16int]
+def FpIADD32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fadd RFP:$src1,
+                                     (sint_to_fp (loadi32 addr:$src2))))]>;
+                // ST(0) = ST(0) + [mem32int]
+def FpIMUL16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fmul RFP:$src1,
+                                     (sint_to_fp (loadi16 addr:$src2))))]>;
+                // ST(0) = ST(0) * [mem16int]
+def FpIMUL32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fmul RFP:$src1,
+                                     (sint_to_fp (loadi32 addr:$src2))))]>;
+                // ST(0) = ST(0) * [mem32int]
+def FpISUB16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fsub RFP:$src1,
+                                     (sint_to_fp (loadi16 addr:$src2))))]>;
+                // ST(0) = ST(0) - [mem16int]
+def FpISUB32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fsub RFP:$src1,
+                                     (sint_to_fp (loadi32 addr:$src2))))]>;
+                // ST(0) = ST(0) - [mem32int]
+def FpISUBR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                     [(set RFP:$dst, (fsub (sint_to_fp (loadi16 addr:$src2)),
+                                      RFP:$src1))]>;
+                // ST(0) = [mem16int] - ST(0)
+def FpISUBR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                     [(set RFP:$dst, (fsub (sint_to_fp (loadi32 addr:$src2)),
+                                      RFP:$src1))]>;
+                // ST(0) = [mem32int] - ST(0)
+def FpIDIV16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fdiv RFP:$src1,
+                                     (sint_to_fp (loadi16 addr:$src2))))]>;
+                // ST(0) = ST(0) / [mem16int]
+def FpIDIV32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                    [(set RFP:$dst, (fdiv RFP:$src1,
+                                     (sint_to_fp (loadi32 addr:$src2))))]>;
+                // ST(0) = ST(0) / [mem32int]
+def FpIDIVR16m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                     [(set RFP:$dst, (fdiv (sint_to_fp (loadi16 addr:$src2)),
+                                      RFP:$src1))]>;
+                // ST(0) = [mem16int] / ST(0)
+def FpIDIVR32m : FpI<(ops RFP:$dst, RFP:$src1, i16mem:$src2), OneArgFPRW,
+                     [(set RFP:$dst, (fdiv (sint_to_fp (loadi32 addr:$src2)),
+                                      RFP:$src1))]>;
+                // ST(0) = [mem32int] / ST(0)
+
+def FIADD16m  : FPI<0xDE, MRM0m, (ops i16mem:$src), "fiadd{s} $src">;
+def FIADD32m  : FPI<0xDA, MRM0m, (ops i32mem:$src), "fiadd{l} $src">;
+def FIMUL16m  : FPI<0xDE, MRM1m, (ops i16mem:$src), "fimul{s} $src">;
+def FIMUL32m  : FPI<0xDA, MRM1m, (ops i32mem:$src), "fimul{l} $src">;
+def FISUB16m  : FPI<0xDE, MRM4m, (ops i16mem:$src), "fisub{s} $src">;
+def FISUB32m  : FPI<0xDA, MRM4m, (ops i32mem:$src), "fisub{l} $src">;
+def FISUBR16m : FPI<0xDE, MRM5m, (ops i16mem:$src), "fisubr{s} $src">;
+def FISUBR32m : FPI<0xDA, MRM5m, (ops i32mem:$src), "fisubr{l} $src">;
+def FIDIV16m  : FPI<0xDE, MRM6m, (ops i16mem:$src), "fidiv{s} $src">;
+def FIDIV32m  : FPI<0xDA, MRM6m, (ops i32mem:$src), "fidiv{s} $src">;
+def FIDIVR16m : FPI<0xDE, MRM7m, (ops i16mem:$src), "fidivr{s} $src">;
+def FIDIVR32m : FPI<0xDA, MRM7m, (ops i32mem:$src), "fidivr{s} $src">;
 
 // NOTE: GAS and apparently all other AT&T style assemblers have a broken notion
 // of some of the 'reverse' forms of the fsub and fdiv instructions.  As such,
@@ -2743,11 +2794,11 @@
 def FpLD64m  : FpI<(ops RFP:$dst, f64mem:$src), ZeroArgFP,
                    [(set RFP:$dst, (loadf64 addr:$src))]>;
 def FpILD16m : FpI<(ops RFP:$dst, i16mem:$src), ZeroArgFP,
-                   []>;
+                   [(set RFP:$dst, (sint_to_fp (loadi16 addr:$src)))]>;
 def FpILD32m : FpI<(ops RFP:$dst, i32mem:$src), ZeroArgFP,
-                   []>;
+                   [(set RFP:$dst, (sint_to_fp (loadi32 addr:$src)))]>;
 def FpILD64m : FpI<(ops RFP:$dst, i64mem:$src), ZeroArgFP,
-                   []>;
+                   [(set RFP:$dst, (X86fild64m addr:$src))]>;
 
 def FpST32m   : FpI<(ops f32mem:$op, RFP:$src), OneArgFP,
                 [(truncstore RFP:$src, addr:$op, f32)]>;






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