[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp README.txt
Nate Begeman
natebegeman at mac.com
Fri Dec 23 17:00:26 PST 2005
Changes in directory llvm/lib/Target/PowerPC:
PPCAsmPrinter.cpp updated: 1.132 -> 1.133
PPCISelDAGToDAG.cpp updated: 1.146 -> 1.147
PPCISelLowering.cpp updated: 1.54 -> 1.55
README.txt updated: 1.41 -> 1.42
---
Log message:
Fix one of the things in the todo file, and get a bit closer to folding
constant offsets from statics into the address arithmetic.
---
Diffs of the changes: (+25 -39)
PPCAsmPrinter.cpp | 1 +
PPCISelDAGToDAG.cpp | 16 +++++++++++++++-
PPCISelLowering.cpp | 5 +++--
README.txt | 42 ++++++------------------------------------
4 files changed, 25 insertions(+), 39 deletions(-)
Index: llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.132 llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.133
--- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1.132 Thu Dec 22 15:15:17 2005
+++ llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp Fri Dec 23 19:00:15 2005
@@ -331,6 +331,7 @@
// Computing the address of a global symbol, not calling it.
GlobalValue *GV = MO.getGlobal();
std::string Name = Mang->getValueName(GV);
+ int offset = MO.getOffset();
// External or weakly linked global variables need non-lazily-resolved stubs
if (!PPCGenerateStaticCode) {
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.146 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.147
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.146 Mon Dec 19 18:26:01 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Dec 23 19:00:15 2005
@@ -927,7 +927,7 @@
break;
}
case ISD::AND: {
- unsigned Imm;
+ unsigned Imm, Imm2;
// If this is an and of a value rotated between 0 and 31 bits and then and'd
// with a mask, emit rlwinm
if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
@@ -947,6 +947,20 @@
return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH),
getI32Imm(MB), getI32Imm(ME));
}
+ // ISD::OR doesn't get all the bitfield insertion fun.
+ // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
+ if (isIntImmediate(N->getOperand(1), Imm) &&
+ N->getOperand(0).getOpcode() == ISD::OR &&
+ isIntImmediate(N->getOperand(0).getOperand(1), Imm2)) {
+ unsigned SH, MB, ME;
+ Imm = ~(Imm^Imm2);
+ if (isRunOfOnes(Imm, MB, ME)) {
+ SDOperand Tmp1 = Select(N->getOperand(0).getOperand(0));
+ SDOperand Tmp2 = Select(N->getOperand(0).getOperand(1));
+ return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2,
+ getI32Imm(SH), getI32Imm(MB), getI32Imm(ME));
+ }
+ }
// Other cases are autogenerated.
break;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.54 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.55
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.54 Thu Dec 22 23:13:35 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp Fri Dec 23 19:00:15 2005
@@ -362,8 +362,9 @@
return Lo;
}
case ISD::GlobalAddress: {
- GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
- SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
+ GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
+ GlobalValue *GV = GSDN->getGlobal();
+ SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
SDOperand Zero = DAG.getConstant(0, MVT::i32);
if (PPCGenerateStaticCode) {
Index: llvm/lib/Target/PowerPC/README.txt
diff -u llvm/lib/Target/PowerPC/README.txt:1.41 llvm/lib/Target/PowerPC/README.txt:1.42
--- llvm/lib/Target/PowerPC/README.txt:1.41 Thu Dec 22 11:19:28 2005
+++ llvm/lib/Target/PowerPC/README.txt Fri Dec 23 19:00:15 2005
@@ -3,10 +3,15 @@
* implement do-loop -> bdnz transform
* implement powerpc-64 for darwin
* use stfiwx in float->int
-* be able to combine sequences like the following into 2 instructions:
+
+* Fold add and sub with constant into non-extern, non-weak addresses so this:
lis r2, ha16(l2__ZTV4Cell)
la r2, lo16(l2__ZTV4Cell)(r2)
addi r2, r2, 8
+becomes:
+ lis r2, ha16(l2__ZTV4Cell+8)
+ la r2, lo16(l2__ZTV4Cell+8)(r2)
+
* Teach LLVM how to codegen this:
unsigned short foo(float a) { return a; }
@@ -24,10 +29,6 @@
rlwinm r3, r2, 0, 16, 31
blr
-and:
- extern int X, Y; int* test(int C) { return C? &X : &Y; }
-as one load when using --enable-pic.
-
* Support 'update' load/store instructions. These are cracked on the G5, but
are still a codesize win.
@@ -170,37 +171,6 @@
===-------------------------------------------------------------------------===
-Compile this (standard bitfield insert of a constant):
-void %test(uint* %tmp1) {
- %tmp2 = load uint* %tmp1 ; <uint> [#uses=1]
- %tmp5 = or uint %tmp2, 257949696 ; <uint> [#uses=1]
- %tmp6 = and uint %tmp5, 4018143231 ; <uint> [#uses=1]
- store uint %tmp6, uint* %tmp1
- ret void
-}
-
-to:
-
-_test:
- lwz r0,0(r3)
- li r2,123
- rlwimi r0,r2,21,3,10
- stw r0,0(r3)
- blr
-
-instead of:
-
-_test:
- lis r2, -4225
- lwz r4, 0(r3)
- ori r2, r2, 65535
- oris r4, r4, 3936
- and r2, r4, r2
- stw r2, 0(r3)
- blr
-
-===-------------------------------------------------------------------------===
-
Compile this:
int %f1(int %a, int %b) {
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