[llvm-commits] CVS: llvm/lib/Target/IA64/IA64.td IA64InstrInfo.td IA64RegisterInfo.td

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64.td updated: 1.3 -> 1.4
IA64InstrInfo.td updated: 1.30 -> 1.31
IA64RegisterInfo.td updated: 1.11 -> 1.12
---
Log message:

update tablegen files - nothing to see here



---
Diffs of the changes:  (+18 -6)

 IA64.td             |    1 +
 IA64InstrInfo.td    |   19 +++++++++++++++----
 IA64RegisterInfo.td |    4 ++--
 3 files changed, 18 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/IA64/IA64.td
diff -u llvm/lib/Target/IA64/IA64.td:1.3 llvm/lib/Target/IA64/IA64.td:1.4
--- llvm/lib/Target/IA64/IA64.td:1.3	Fri Sep 30 01:42:24 2005
+++ llvm/lib/Target/IA64/IA64.td	Wed Dec 21 21:56:03 2005
@@ -47,6 +47,7 @@
 
 //  r1, // global data pointer (GP)  - XXX NOT callee saved, we do it ourselves
 //  r12, // memory stack pointer (SP)- XXX NOT callee saved, we do it ourselves
+//  rp, // return branch register (rp/b0) - we do this ourselves
   // **** r13 (thread pointer) we do not touch, ever. it's not here. ****//
   //r15, // our frame pointer (FP)
   


Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.30 llvm/lib/Target/IA64/IA64InstrInfo.td:1.31
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.30	Sun Dec  4 20:34:29 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td	Wed Dec 21 21:56:03 2005
@@ -23,7 +23,7 @@
 def s14imm  : Operand<i64> {
   let PrintMethod = "printS14ImmOperand";
 }
-def s22imm  : Operand<i32> {
+def s22imm  : Operand<i64> {
   let PrintMethod = "printS22ImmOperand";
 }
 def u64imm  : Operand<i64> {
@@ -116,7 +116,12 @@
 def ADDL_GA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, globaladdress:$imm),
            "addl $dst = $imm, $src1;;",
 	   []>;
-  
+
+// hmm 
+def ADDL_EA : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, calltarget:$imm),
+           "addl $dst = $imm, $src1;;",
+	   []>;
+ 
 def SUB  : AForm_DAG<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
            "sub $dst = $src1, $src2;;",
 	   [(set GR:$dst, (sub GR:$src1, GR:$src2))]>;
@@ -639,7 +644,7 @@
     "($qp) br.cond.sptk $dst;;">;
 }
 
-let isCall = 1, isTerminator = 1, isBranch = 1, 
+let isCall = 1, /* isTerminator = 1, isBranch = 1, */
   Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
 // all calls clobber non-callee-saved registers, and for now, they are these:
   Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
@@ -659,8 +664,14 @@
   def BRCALL: RawForm<0x03, 0xb0, (ops calltarget:$dst),
   "br.call.sptk rp = $dst;;">;       // FIXME: teach llvm about branch regs?
 // new daggy stuff!  
-  def BRCALL_IPREL : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops),
+
+// calls a globaladdress
+  def BRCALL_IPREL_GA : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops),
+  "br.call.sptk rp = $dst;;">;       // FIXME: teach llvm about branch regs?
+// calls an externalsymbol
+  def BRCALL_IPREL_ES : RawForm<0x03, 0xb0, (ops calltarget:$dst, variable_ops),
   "br.call.sptk rp = $dst;;">;       // FIXME: teach llvm about branch regs?
+// calls through a function descriptor
   def BRCALL_INDIRECT : RawForm<0x03, 0xb0, (ops GR:$branchreg, variable_ops),
   "br.call.sptk rp = $branchreg;;">; // FIXME: teach llvm about branch regs?
   def BRLCOND_CALL : RawForm<0x03, 0xb0, (ops PR:$qp, i64imm:$dst),


Index: llvm/lib/Target/IA64/IA64RegisterInfo.td
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.td:1.11 llvm/lib/Target/IA64/IA64RegisterInfo.td:1.12
--- llvm/lib/Target/IA64/IA64RegisterInfo.td:1.11	Wed Nov 30 22:51:06 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.td	Wed Dec 21 21:56:03 2005
@@ -235,8 +235,8 @@
 def GR : RegisterClass<"IA64", [i64], 64, 
        [
        
-//FIXME!: for readability, we don't want the out registers to be the first
-//        ones allocated
+//FIXME!: for both readability and performance, we don't want the out
+//        registers to be the first ones allocated
 
         out7, out6, out5, out4, out3, out2, out1, out0,
         r3,  r8,  r9,  r10, r11, r14,