[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td SparcV8ISelSimple.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV8:

SparcV8InstrInfo.td updated: 1.70 -> 1.71
SparcV8ISelSimple.cpp updated: 1.94 -> 1.95
---
Log message:

Eliminate CMPri, which is a synonym for SUBCCri


---
Diffs of the changes:  (+3 -8)

 SparcV8ISelSimple.cpp |    2 +-
 SparcV8InstrInfo.td   |    9 ++-------
 2 files changed, 3 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.td
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.70 llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.71
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.td:1.70	Sat Dec 17 17:20:27 2005
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.td	Sat Dec 17 17:52:08 2005
@@ -94,13 +94,6 @@
     def RETL: F3_2<2, 0b111000, (ops),
                    "retl", [(ret)]>;
 }
-// CMP is a special case of SUBCC where destination is ignored, by setting it to
-// %g0 (hardwired zero).
-// FIXME: should keep track of the fact that it defs the integer condition codes
-let rd = 0 in
-  def CMPri: F3_2<2, 0b010100,
-                  (ops IntRegs:$b, i32imm:$c),
-                  "cmp $b, $c", []>;
 
 // Section B.1 - Load Integer Instructions, p. 90
 def LDSBrr : F3_1<3, 0b001001,
@@ -520,6 +513,8 @@
                  (ops FPRegs:$dst, FPRegs:$src),
                  "fabss $src, $dst",
                  [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
+// FIXME: ADD FNEGD/FABSD pseudo instructions.
+
 
 // Floating-point Square Root Instructions, p.145
 def FSQRTS : F3_3<2, 0b110100, 0b000101001, 


Index: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.94 llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.95
--- llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.94	Sat Dec 17 16:22:53 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp	Sat Dec 17 17:52:08 2005
@@ -1062,7 +1062,7 @@
       // CondReg=(<condition>);
       // If (CondReg==0) goto notTakenSuccMBB;
       unsigned CondReg = getReg (I.getCondition ());
-      BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
+      BuildMI (BB, V8::SUBCCri, 2, V8::G0).addReg(CondReg).addSImm(0);
       BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
       BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
       return;