[llvm-commits] Re: llvm-commits Digest, Vol 18, Issue 8

[Andrew Lenharth]

> Message: 1
> Date: Wed, 7 Dec 2005 12:02:16 -0600
> From: "Chris Lattner" <lattner at cs.uiuc.edu>
> Subject: [llvm-commits] CVS:
> 	llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp 
> To: llvm-commits at cs.uiuc.edu
> Message-ID: <200512071802.MAA03176 at zion.cs.uiuc.edu>

> Changes in directory llvm/lib/CodeGen/SelectionDAG:
> 
> DAGCombiner.cpp updated: 1.63 -> 1.64
> ---
> Log message:
> 
> Only transform (sext (truncate x)) -> (sextinreg x) if before legalize or
> if the target supports the resultant sextinreg

I think it is this change that breaks thing.  This leads to i32 =
sign_extend_inreg hitting promoteOp, which cannot deal with it.

reduction for alpha:

;ModuleID = 'bugpoint-reduced-simplified.bc'
target endian = little
target pointersize = 64
%id.0__ = external global ushort

implementation   ; Functions:

fastcc void %dxi_send() {
entry:
        %tmp.233 = load ushort* %id.0__ 
        %tmp.234 = cast ushort %tmp.233 to int
        %tmp.235 = load short* null
        %tmp.236 = cast short %tmp.235 to ushort
        %tmp.244 = cast ushort %tmp.236 to int
        %tmp.245 = shl int %tmp.244, ubyte 8
        %tmp.247 = and int %tmp.245, 65280
        %tmp.248 = or int 0, %tmp.247
        %tmp.249 = cast int %tmp.248 to short
        %tmp.250 = cast short %tmp.249 to int
        %tmp.251 = seteq int %tmp.234, %tmp.250
        br bool %tmp.251, label %endif.20, label %then.20

then.20:                ; preds = %entry
        ret void

endif.20:               ; preds = %entry
        call void %llvm.memcpy( sbyte* null, sbyte* null, ulong 8, uint
1 )
        unreachable
}

declare void %llvm.memcpy(sbyte*, sbyte*, ulong, uint)


> 
> ---
> Diffs of the changes:  (+3 -1)
> 
>  DAGCombiner.cpp |    4 +++-
>  1 files changed, 3 insertions(+), 1 deletion(-)
> 
> 
> Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
> diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.64
> --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.63	Wed Dec  7 01:11:03 2005
> +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Wed Dec  7 12:02:05 2005
> @@ -1547,7 +1547,9 @@
>    if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
>      return N0;
>    // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size.
> -  if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT)
> +  if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&&
> +      (!AfterLegalize || 
> +       TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType())))
>      return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0),
>                         DAG.getValueType(N0.getValueType()));
>    // fold (sext (load x)) -> (sextload x)