[llvm-commits] CVS: llvm/utils/TableGen/TableGen.cpp

[Jim Laskey]

Changes in directory llvm/utils/TableGen:

TableGen.cpp updated: 1.39 -> 1.40
---
Log message:

Plugin new subtarget backend into the build.


---
Diffs of the changes:  (+7 -0)

 TableGen.cpp |    7 +++++++
 1 files changed, 7 insertions(+)


Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.39 llvm/utils/TableGen/TableGen.cpp:1.40
--- llvm/utils/TableGen/TableGen.cpp:1.39	Fri Sep  2 20:14:03 2005
+++ llvm/utils/TableGen/TableGen.cpp	Fri Oct 21 14:02:44 2005
@@ -25,6 +25,7 @@
 #include "AsmWriterEmitter.h"
 #include "InstrSelectorEmitter.h"
 #include "DAGISelEmitter.h"
+#include "SubtargetEmitter.h"
 #include <algorithm>
 #include <cstdio>
 #include <fstream>
@@ -36,6 +37,7 @@
   GenRegisterEnums, GenRegister, GenRegisterHeader,
   GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
   GenDAGISel,
+  GenSubtarget,
   PrintEnums,
   Parse
 };
@@ -63,6 +65,8 @@
                                "Generate an instruction selector"),
                     clEnumValN(GenDAGISel, "gen-dag-isel",
                                "Generate a DAG instruction selector"),
+                    clEnumValN(GenSubtarget, "gen-subtarget",
+                               "Generate subtarget enumerations"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValN(Parse, "parse",
@@ -472,6 +476,9 @@
     case GenDAGISel:
       DAGISelEmitter(Records).run(*Out);
       break;
+    case GenSubtarget:
+      SubtargetEmitter(Records).run(*Out);
+      break;
     case PrintEnums:
     {
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);