[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp PPCISelLowering.cpp PPCISelLowering.h

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPCISelDAGToDAG.cpp updated: 1.108 -> 1.109
PPCISelLowering.cpp updated: 1.33 -> 1.34
PPCISelLowering.h updated: 1.8 -> 1.9
---
Log message:

Add the ability to lower return instructions to TargetLowering.  This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).


---
Diffs of the changes:  (+32 -5)

 PPCISelDAGToDAG.cpp |   21 ++++++++++++++++-----
 PPCISelLowering.cpp |   13 +++++++++++++
 PPCISelLowering.h   |    3 +++
 3 files changed, 32 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.108 llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.109
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1.108	Mon Oct 17 19:28:58 2005
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp	Tue Oct 18 18:23:37 2005
@@ -1206,6 +1206,22 @@
       
     // Other cases are autogenerated.
     break;
+  case ISD::ANY_EXTEND:
+    switch(N->getValueType(0)) {
+    default: assert(0 && "Unhandled type in ANY_EXTEND");
+    case MVT::i64:
+      CurDAG->SelectNodeTo(N, PPC::OR8, MVT::i64, Select(N->getOperand(0)), 
+                           Select(N->getOperand(0)));
+      break;
+    }
+    return SDOperand(N, 0);
+  case ISD::ZERO_EXTEND:
+    assert(N->getValueType(0) == MVT::i64 && 
+           N->getOperand(0).getValueType() == MVT::i32 &&
+           "ZERO_EXTEND only supported for i32 -> i64");
+    CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Select(N->getOperand(0)),
+                         getI32Imm(32));
+    return SDOperand(N, 0);
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
@@ -1393,11 +1409,6 @@
       SDOperand Val = Select(N->getOperand(1));
       if (N->getOperand(1).getValueType() == MVT::i32) {
         Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
-      } else if (N->getOperand(1).getValueType() == MVT::i64) {
-        SDOperand Srl = CurDAG->getTargetNode(PPC::RLDICL, MVT::i64, Val,
-                                              getI32Imm(32), getI32Imm(32));
-        Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
-        Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Srl);
       } else {
         assert(MVT::isFloatingPoint(N->getOperand(1).getValueType()));
         Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);


Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.33 llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.34
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp:1.33	Mon Oct 17 19:56:42 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp	Tue Oct 18 18:23:37 2005
@@ -693,6 +693,19 @@
   return std::make_pair(RetVal, Chain);
 }
 
+SDOperand PPCTargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
+                                           SelectionDAG &DAG) {
+  if (Op.getValueType() == MVT::i64) {
+    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 
+                               DAG.getConstant(1, MVT::i32));
+    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
+                               DAG.getConstant(0, MVT::i32));
+    return DAG.getNode(ISD::RET, MVT::Other, Chain, Lo, Hi);
+  } else {
+    return DAG.getNode(ISD::RET, MVT::Other, Chain, Op);
+  }
+}
+
 SDOperand PPCTargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
                                           Value *VAListV, SelectionDAG &DAG) {
   // vastart just stores the address of the VarArgsFrameIndex slot into the


Index: llvm/lib/Target/PowerPC/PPCISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPCISelLowering.h:1.8 llvm/lib/Target/PowerPC/PPCISelLowering.h:1.9
--- llvm/lib/Target/PowerPC/PPCISelLowering.h:1.8	Sun Oct 16 00:39:50 2005
+++ llvm/lib/Target/PowerPC/PPCISelLowering.h	Tue Oct 18 18:23:37 2005
@@ -63,6 +63,9 @@
                   unsigned CC,
                   bool isTailCall, SDOperand Callee, ArgListTy &Args,
                   SelectionDAG &DAG);
+
+    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
+                                    SelectionDAG &DAG);
     
     virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
                                    Value *VAListV, SelectionDAG &DAG);