[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.199 -> 1.200
---
Log message:

fix indentation


---
Diffs of the changes:  (+57 -57)

 SelectionDAG.cpp |  114 +++++++++++++++++++++++++++----------------------------
 1 files changed, 57 insertions(+), 57 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.199 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.200
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.199	Fri Oct  7 01:10:46 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Oct  7 01:37:02 2005
@@ -591,63 +591,63 @@
   
   // If we know the result of a setcc has the top bits zero, use this info.
   switch (Op.getOpcode()) {
-    case ISD::Constant:
-      return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
-      
-    case ISD::SETCC:
-      return ((Mask & 1) == 0) &&
-      TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
-      
-    case ISD::ZEXTLOAD:
-      SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
-      return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
-    case ISD::ZERO_EXTEND:
-      SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
-      return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
-    case ISD::AssertZext:
-      SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
-      return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
-    case ISD::AND:
-      // (X & C1) & C2 == 0   iff   C1 & C2 == 0.
-      if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
-        return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
-      
-      // FALL THROUGH
-    case ISD::OR:
-    case ISD::XOR:
-      return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
-      MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
-    case ISD::SELECT:
-      return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
-      MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
-    case ISD::SELECT_CC:
-      return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
-      MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
-    case ISD::SRL:
-      // (ushr X, C1) & C2 == 0   iff  X & (C2 << C1) == 0
-      if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
-        uint64_t NewVal = Mask << ShAmt->getValue();
-        SrcBits = MVT::getSizeInBits(Op.getValueType());
-        if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
-        return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
-      }
-      return false;
-    case ISD::SHL:
-      // (ushl X, C1) & C2 == 0   iff  X & (C2 >> C1) == 0
-      if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
-        uint64_t NewVal = Mask >> ShAmt->getValue();
-        return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
-      }
-      return false;
-    case ISD::CTTZ:
-    case ISD::CTLZ:
-    case ISD::CTPOP:
-      // Bit counting instructions can not set the high bits of the result
-      // register.  The max number of bits sets depends on the input.
-      return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
-      
-      // TODO we could handle some SRA cases here.
-    default: break;
+  case ISD::Constant:
+    return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
+    
+  case ISD::SETCC:
+    return ((Mask & 1) == 0) &&
+    TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
+    
+  case ISD::ZEXTLOAD:
+    SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
+    return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
+  case ISD::ZERO_EXTEND:
+    SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
+    return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
+  case ISD::AssertZext:
+    SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
+    return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
+  case ISD::AND:
+    // (X & C1) & C2 == 0   iff   C1 & C2 == 0.
+    if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
+      return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
+    
+    // FALL THROUGH
+  case ISD::OR:
+  case ISD::XOR:
+    return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
+           MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
+  case ISD::SELECT:
+    return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
+           MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
+  case ISD::SELECT_CC:
+    return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
+           MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
+  case ISD::SRL:
+    // (ushr X, C1) & C2 == 0   iff  X & (C2 << C1) == 0
+    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      uint64_t NewVal = Mask << ShAmt->getValue();
+      SrcBits = MVT::getSizeInBits(Op.getValueType());
+      if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
+      return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
+    }
+    return false;
+  case ISD::SHL:
+    // (ushl X, C1) & C2 == 0   iff  X & (C2 >> C1) == 0
+    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      uint64_t NewVal = Mask >> ShAmt->getValue();
+      return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
+    }
+    return false;
+  case ISD::CTTZ:
+  case ISD::CTLZ:
+  case ISD::CTPOP:
+    // Bit counting instructions can not set the high bits of the result
+    // register.  The max number of bits sets depends on the input.
+    return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
+    
+    // TODO we could handle some SRA cases here.
+  default: break;
   }
   
   return false;