[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

DAGCombiner.cpp updated: 1.19 -> 1.20
SelectionDAG.cpp updated: 1.198 -> 1.199
---
Log message:

Turn sdivs into udivs when we can prove the sign bits are clear.  This
implements CodeGen/PowerPC/div-2.ll


---
Diffs of the changes:  (+21 -0)

 DAGCombiner.cpp  |   10 ++++++++++
 SelectionDAG.cpp |   11 +++++++++++
 2 files changed, 21 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.19 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.20
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1.19	Wed Oct  5 16:43:42 2005
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp	Fri Oct  7 01:10:46 2005
@@ -501,6 +501,7 @@
 SDOperand DAGCombiner::visitSDIV(SDNode *N) {
   SDOperand N0 = N->getOperand(0);
   SDOperand N1 = N->getOperand(1);
+  MVT::ValueType VT = N->getValueType(0);
   ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
 
@@ -508,6 +509,15 @@
   if (N0C && N1C && !N1C->isNullValue())
     return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
                            N->getValueType(0));
+
+  // If we know the sign bits of both operands are zero, strength reduce to a
+  // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
+  uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
+  if (MaskedValueIsZero(N1, SignBit, TLI) &&
+      MaskedValueIsZero(N0, SignBit, TLI))
+    return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
+  
+  
   return SDOperand();
 }
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.198 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.199
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.198	Wed Oct  5 16:44:43 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Oct  7 01:10:46 2005
@@ -1556,6 +1556,17 @@
       return N1;
     }
     break;
+  case ISD::SDIV: {
+    if (CombinerEnabled) break;
+    
+    // If we know the sign bits of both operands are zero, strength reduce to a
+    // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
+    uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
+    if (MaskedValueIsZero(N2, SignBit, TLI) &&
+        MaskedValueIsZero(N1, SignBit, TLI))
+      return getNode(ISD::UDIV, VT, N1, N2);
+    break;
+  }   
 
   case ISD::AND:
   case ISD::OR: