[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen:

VirtRegMap.cpp updated: 1.41 -> 1.42
---
Log message:

Fix the LLC regressions on X86 last night.  In particular, when undoing
previous copy elisions and we discover we need to reload a register, make
sure to use the regclass of the original register for the reload, not the
class of the current register.  This avoid using 16-bit loads to reload 32-bit
values.


---
Diffs of the changes:  (+12 -5)

 VirtRegMap.cpp |   17 ++++++++++++-----
 1 files changed, 12 insertions(+), 5 deletions(-)


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.41 llvm/lib/CodeGen/VirtRegMap.cpp:1.42
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.41	Wed Oct  5 13:30:19 2005
+++ llvm/lib/CodeGen/VirtRegMap.cpp	Thu Oct  6 12:19:06 2005
@@ -266,9 +266,14 @@
 
     // AssignedPhysReg - The physreg that was assigned for use by the reload.
     unsigned AssignedPhysReg;
-
-    ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr)
-      : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {}
+    
+    // VirtReg - The virtual register itself.
+    unsigned VirtReg;
+
+    ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
+             unsigned vreg)
+      : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
+      VirtReg(vreg) {}
   };
 }
 
@@ -381,7 +386,7 @@
         // case, we actually insert a reload for V1 in R1, ensuring that
         // we can get at R0 or its alias.
         ReusedOperands.push_back(ReusedOp(i, StackSlot, PhysReg,
-                                          VRM.getPhys(VirtReg)));
+                                          VRM.getPhys(VirtReg), VirtReg));
         ++NumReused;
         continue;
       }
@@ -409,8 +414,10 @@
               // Okay, we found out that an alias of a reused register
               // was used.  This isn't good because it means we have
               // to undo a previous reuse.
+              const TargetRegisterClass *AliasRC =
+                MBB.getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
               MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
-                                        Op.StackSlot, RC);
+                                        Op.StackSlot, AliasRC);
               ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
                              PhysRegsAvailable);