[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp PPC32ISelPattern.cpp PowerPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.91 -> 1.92
PPC32ISelPattern.cpp updated: 1.181 -> 1.182
PowerPCInstrInfo.td updated: 1.115 -> 1.116
---
Log message:

fsel can take a different FP type for the comparison and for the result.  As such
split the FSEL family into 4 things instead of just two.


---
Diffs of the changes:  (+37 -22)

 PPC32ISelDAGToDAG.cpp |   25 ++++++++++++++-----------
 PPC32ISelPattern.cpp  |    7 +++++--
 PowerPCInstrInfo.td   |   27 ++++++++++++++++++---------
 3 files changed, 37 insertions(+), 22 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.91 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.92
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.91	Sat Oct  1 18:06:26 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Oct  2 01:58:23 2005
@@ -752,18 +752,21 @@
     CodeGenMap[Op.getValue(1)] = Result.getValue(1);
     return SDOperand(Result.Val, Op.ResNo);
   }      
-  case PPCISD::FSEL:
-    if (N->getValueType(0) == MVT::f32)
-      CurDAG->SelectNodeTo(N, PPC::FSELS, MVT::f32,
-                           Select(N->getOperand(0)),
-                           Select(N->getOperand(1)),
-                           Select(N->getOperand(2)));
-    else
-      CurDAG->SelectNodeTo(N, PPC::FSELD, MVT::f64,
-                           Select(N->getOperand(0)),
-                           Select(N->getOperand(1)),
-                           Select(N->getOperand(2)));
+  case PPCISD::FSEL: {
+    unsigned Opc;
+    if (N->getValueType(0) == MVT::f32) {
+      Opc = N->getOperand(0).getValueType() == MVT::f32 ?
+              PPC::FSELSS : PPC::FSELSD;
+    } else {
+      Opc = N->getOperand(0).getValueType() == MVT::f64 ?
+              PPC::FSELDD : PPC::FSELDS;
+    }
+    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
+                         Select(N->getOperand(0)),
+                         Select(N->getOperand(1)),
+                         Select(N->getOperand(2)));
     return SDOperand(N, 0);
+  }
   case PPCISD::FCFID:
     CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0),
                          Select(N->getOperand(0)));


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.181 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.182
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.181	Fri Sep 30 20:35:02 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Sun Oct  2 01:58:23 2005
@@ -816,9 +816,12 @@
     Tmp2 = SelectExpr(N.getOperand(1));
     Tmp3 = SelectExpr(N.getOperand(2));
     if (N.getOperand(0).getValueType() == MVT::f32)
-      BuildMI(BB, PPC::FSELS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+      Opc = N.getOperand(0).getValueType() == MVT::f32 ?
+        PPC::FSELSS : PPC::FSELSD;
     else
-      BuildMI(BB, PPC::FSELD, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+      Opc = N.getOperand(0).getValueType() == MVT::f64 ?
+        PPC::FSELDD : PPC::FSELDS;
+    BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
     return Result;
   case PPCISD::FCFID:
     Tmp1 = SelectExpr(N.getOperand(0));


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.115 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.116
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.115	Fri Sep 30 20:34:18 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Sun Oct  2 01:58:23 2005
@@ -791,15 +791,24 @@
                     (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
                     "fnmsubs $FRT, $FRA, $FRC, $FRB",
                     []>;
-// FSEL is artificially split into 4 and 8-byte forms.
-def FSELD : AForm_1<63, 23,
-                    (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
-                    "fsel $FRT, $FRA, $FRC, $FRB",
-                    []>;
-def FSELS : AForm_1<63, 23,
-                    (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
-                    "fsel $FRT, $FRA, $FRC, $FRB",
-                    []>;
+// FSEL is artificially split into 4 and 8-byte forms for the comparison type
+// and 4/8 byte forms for the result and operand type..
+def FSELDD : AForm_1<63, 23,
+                     (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
+def FSELSS : AForm_1<63, 23,
+                     (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
+def FSELDS : AForm_1<63, 23,  // result Double, comparison Single
+                     (ops F8RC:$FRT, F4RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
+def FSELSD : AForm_1<63, 23,  // result Single, comparison Double
+                     (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
+                     "fsel $FRT, $FRA, $FRC, $FRB",
+                     []>;
 def FADD  : AForm_2<63, 21,
                     (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRB),
                     "fadd $FRT, $FRA, $FRB",