[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.86 -> 1.87
---
Log message:

Remove code for patterns that are autogenerated


---
Diffs of the changes:  (+9 -30)

 PPC32ISelDAGToDAG.cpp |   39 +++++++++------------------------------
 1 files changed, 9 insertions(+), 30 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.86 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.87
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.86	Wed Sep 28 19:59:32 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Sep 29 18:33:31 2005
@@ -847,9 +847,8 @@
       }
     }
     
-    CurDAG->SelectNodeTo(N, PPC::DIVW, MVT::i32, Select(N->getOperand(0)),
-                         Select(N->getOperand(1)));
-    return SDOperand(N, 0);
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::UDIV: {
     // If this is a divide by constant, we can emit code using some magic
@@ -861,9 +860,8 @@
       return Result;
     }
     
-    CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)),
-                         Select(N->getOperand(1)));
-    return SDOperand(N, 0);
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::AND: {
     unsigned Imm;
@@ -884,18 +882,9 @@
                            getI32Imm(MB), getI32Imm(ME));
       return SDOperand(N, 0);
     }
-    // Finally, check for the case where we are being asked to select
-    // and (not(a), b) or and (a, not(b)) which can be selected as andc.
-    if (isOprNot(N->getOperand(0).Val))
-      CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(1)),
-                           Select(N->getOperand(0).getOperand(0)));
-    else if (isOprNot(N->getOperand(1).Val))
-      CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(0)),
-                           Select(N->getOperand(1).getOperand(0)));
-    else
-      CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)),
-                           Select(N->getOperand(1)));
-    return SDOperand(N, 0);
+    
+    // Other cases are autogenerated.
+    break;
   }
   case ISD::OR:
     if (SDNode *I = SelectBitfieldInsert(N))
@@ -906,18 +895,8 @@
                                            PPC::ORIS, PPC::ORI))
       return CodeGenMap[Op] = SDOperand(I, 0);
       
-    // Finally, check for the case where we are being asked to select
-    // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc.
-    if (isOprNot(N->getOperand(0).Val))
-      CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(1)),
-                           Select(N->getOperand(0).getOperand(0)));
-    else if (isOprNot(N->getOperand(1).Val))
-      CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(0)),
-                           Select(N->getOperand(1).getOperand(0)));
-    else
-      CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)),
-                           Select(N->getOperand(1)));
-    return SDOperand(N, 0);
+    // Other cases are autogenerated.
+    break;
   case ISD::SHL: {
     unsigned Imm, SH, MB, ME;
     if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&