[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp

Chris Lattner lattner at cs.uiuc.edu
Wed Sep 28 15:53:28 PDT 2005



Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.84 -> 1.85
---
Log message:

Autogen MUL, move FP cases together


---
Diffs of the changes:  (+12 -24)

 PPC32ISelDAGToDAG.cpp |   36 ++++++++++++------------------------
 1 files changed, 12 insertions(+), 24 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.84 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.85
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.84	Wed Sep 28 17:50:24 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Sep 28 17:53:16 2005
@@ -820,23 +820,6 @@
                          Select(N->getOperand(1)));
     return SDOperand(N, 0);
   }
-  case ISD::MUL: {
-    unsigned Imm, Opc;
-    if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) {
-      CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32,
-                           Select(N->getOperand(0)), getI32Imm(Lo16(Imm)));
-      return SDOperand(N, 0);
-    } 
-    CurDAG->SelectNodeTo(N, PPC::MULLW, MVT::i32, Select(N->getOperand(0)), 
-                         Select(N->getOperand(1)));
-    return SDOperand(N, 0);
-  }
-  case ISD::FMUL: {
-    unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
-    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)), 
-                         Select(N->getOperand(1)));
-    return SDOperand(N, 0);
-  } 
   case ISD::SDIV: {
     unsigned Imm;
     if (isIntImmediate(N->getOperand(1), Imm)) {
@@ -871,13 +854,6 @@
                          Select(N->getOperand(1)));
     return SDOperand(N, 0);
   }
-  case ISD::FDIV: {
-    unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
-    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)), 
-                         Select(N->getOperand(1)));
-    return SDOperand(N, 0);
-  } 
-    
   case ISD::UDIV: {
     // If this is a divide by constant, we can emit code using some magic
     // constants to implement it as a multiply instead.
@@ -997,6 +973,18 @@
                            Select(N->getOperand(1)));
     return SDOperand(N, 0);
   }
+  case ISD::FMUL: {
+    unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FMULS : PPC::FMUL;
+    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)), 
+                         Select(N->getOperand(1)));
+    return SDOperand(N, 0);
+  } 
+  case ISD::FDIV: {
+    unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FDIVS : PPC::FDIV;
+    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)), 
+                         Select(N->getOperand(1)));
+    return SDOperand(N, 0);
+  } 
   case ISD::FABS:
     CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0), 
                          Select(N->getOperand(0)));






More information about the llvm-commits mailing list