[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp PPC32RegisterInfo.h

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.cpp updated: 1.21 -> 1.22
PPC32RegisterInfo.h updated: 1.3 -> 1.4
---
Log message:

Fix a problem that Nate noticed, where spill code was not getting coallesced
with copies, leading to code like this:

       lwz r4, 380(r1)
       or r10, r4, r4    ;; Last use of r4

By teaching the PPC backend how to fold spills into copies, we now get this 
code:

       lwz r10, 380(r1)

wow. :)

This reduces a testcase nate sent me from 1505 instructions to 1484.

Note that this could handle FP values but doesn't currently, for reasons
mentioned in the patch



---
Diffs of the changes:  (+32 -0)

 PPC32RegisterInfo.cpp |   27 +++++++++++++++++++++++++++
 PPC32RegisterInfo.h   |    5 +++++
 2 files changed, 32 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.21 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.22
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.21	Fri Sep  9 15:51:08 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Fri Sep  9 16:46:49 2005
@@ -134,6 +134,33 @@
   }
 }
 
+/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
+/// copy instructions, turning them into load/store instructions.
+MachineInstr *PPC32RegisterInfo::foldMemoryOperand(MachineInstr *MI,
+                                                   unsigned OpNum,
+                                                   int FrameIndex) const {
+  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
+  // it takes more than one instruction to store it.
+  unsigned Opc = MI->getOpcode();
+  
+  if ((Opc == PPC::OR &&
+       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
+    if (OpNum == 0) {  // move -> store
+      unsigned InReg = MI->getOperand(1).getReg();
+      return addFrameReference(BuildMI(PPC::STW,
+                                       3).addReg(InReg), FrameIndex);
+    } else {
+      unsigned OutReg = MI->getOperand(0).getReg();
+      return addFrameReference(BuildMI(PPC::LWZ, 2, OutReg), FrameIndex);
+    }
+    
+  } else if (Opc == PPC::FMR) {
+    // FIXME: We would be able to fold this, but we don't know whether to use a
+    // 32- or 64-bit load/store :(.
+  }
+  return 0;
+}
+
 //===----------------------------------------------------------------------===//
 // Stack Frame Processing methods
 //===----------------------------------------------------------------------===//


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.h
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.3 llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.4
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.h:1.3	Fri Aug 19 13:30:39 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.h	Fri Sep  9 16:46:49 2005
@@ -40,6 +40,11 @@
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;
 
+  /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
+  /// copy instructions, turning them into load/store instructions.
+  virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
+                                          int FrameIndex) const;
+  
   void eliminateCallFramePseudoInstr(MachineFunction &MF,
                                      MachineBasicBlock &MBB,
                                      MachineBasicBlock::iterator I) const;