[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.cpp updated: 1.20 -> 1.21
---
Log message:

code cleanup


---
Diffs of the changes:  (+3 -2)

 PPC32RegisterInfo.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.20 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.21
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.20	Fri Aug 26 16:51:29 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Fri Sep  9 15:51:08 2005
@@ -214,8 +214,9 @@
     // convert into indexed form of the instruction
     // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
     // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
-    unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
-    assert(NewOpcode && "No indexed form of load or store available!");
+    assert(ImmToIdxMap.count(MI.getOpcode()) &&
+           "No indexed form of load or store available!");
+    unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
     MI.setOpcode(NewOpcode);
     MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
     MI.SetMachineOperandReg(2, PPC::R0);