[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PowerPCInstrInfo.td updated: 1.94 -> 1.95
---
Log message:

whitespace/comment changes, no functionality diffs


---
Diffs of the changes:  (+5 -2)

 PowerPCInstrInfo.td |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.94 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.95
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.94	Thu Sep  8 14:50:41 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Thu Sep  8 18:17:26 2005
@@ -17,7 +17,8 @@
 //===----------------------------------------------------------------------===//
 // Selection DAG Type Constraint definitions.
 //
-// Note that the semantics of these constraints are hard coded into tblgen.
+// Note that the semantics of these constraints are hard coded into tblgen.  To
+// modify or add constraints, you have to hack tblgen.
 //
 
 class SDTypeConstraint<int opnum> {
@@ -66,7 +67,9 @@
 // Builtin profiles.
 def SDTImm   : SDTypeProfile<1, 0, [SDTCisInt<0>]>;      // for 'imm'.
 def SDTVT    : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'
-def SDTBinOp : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]>;
+def SDTBinOp : SDTypeProfile<1, 2, [      // add, mul, etc.
+  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>
+]>;
 def SDTIntBinOp : SDTypeProfile<1, 2, [   // and, or, xor, udiv, etc.
   SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
 ]>;