[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Nate Begeman]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.178 -> 1.179
---
Log message:

Fix a mistake in my previous patch pointed out by sabre; the AssertZext
case in MaskedValueIsZero was wrong.


---
Diffs of the changes:  (+3 -2)

 SelectionDAG.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.178 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.179
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.178	Tue Aug 30 19:27:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug 30 19:43:08 2005
@@ -1095,10 +1095,11 @@
     SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
     return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
   case ISD::ZERO_EXTEND:
-  case ISD::AssertZext:
     SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
     return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
-
+  case ISD::AssertZext:
+    SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
+    return (Mask & ((1ULL << SrcBits)-1) == 0; // Returning only the zext bits.
   case ISD::AND:
     // (X & C1) & C2 == 0   iff   C1 & C2 == 0.
     if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))