[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32RegisterInfo.cpp updated: 1.19 -> 1.20
---
Log message:

teach getClass what a condition reg is


---
Diffs of the changes:  (+5 -3)

 PPC32RegisterInfo.cpp |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.19 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.20
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.19	Fri Aug 26 16:49:18 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Fri Aug 26 16:51:29 2005
@@ -44,10 +44,12 @@
 }
 
 static const TargetRegisterClass *getClass(unsigned SrcReg) {
+  if (PPC32::GPRCRegisterClass->contains(SrcReg))
+    return PPC32::GPRCRegisterClass;
   if (PPC32::FPRCRegisterClass->contains(SrcReg))
     return PPC32::FPRCRegisterClass;
-  assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
-  return PPC32::GPRCRegisterClass;
+  assert(PPC32::CRRCRegisterClass->contains(SrcReg) &&"Reg not FPR, GPR, CRRC");
+  return PPC32::CRRCRegisterClass;
 }
 
 static unsigned getIdx(const TargetRegisterClass *RC) {
@@ -101,7 +103,7 @@
   static const unsigned Opcode[] = {
     PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LFS, PPC::LFD
   };
-  const TargetRegisterClass *RegClass = getClass(SrcReg);
+  const TargetRegisterClass *RegClass = getClass(DestReg);
   unsigned OC = Opcode[getIdx(RegClass)];
   if (DestReg == PPC::LR) {
     addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);