[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp PPC32ISelDAGToDAG.cpp PPC32ISelPattern.cpp PowerPCBranchSelector.cpp PowerPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32CodeEmitter.cpp updated: 1.33 -> 1.34
PPC32ISelDAGToDAG.cpp updated: 1.23 -> 1.24
PPC32ISelPattern.cpp updated: 1.162 -> 1.163
PowerPCBranchSelector.cpp updated: 1.12 -> 1.13
PowerPCInstrInfo.td updated: 1.79 -> 1.80
---
Log message:

Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class.  Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.


---
Diffs of the changes:  (+21 -7)

 PPC32CodeEmitter.cpp      |    3 ++-
 PPC32ISelDAGToDAG.cpp     |    7 ++++++-
 PPC32ISelPattern.cpp      |   12 +++++++++---
 PowerPCBranchSelector.cpp |    3 ++-
 PowerPCInstrInfo.td       |    3 ++-
 5 files changed, 21 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.33 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.34
--- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.33	Wed Jul 27 01:12:33 2005
+++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp	Wed Aug 24 18:08:16 2005
@@ -124,7 +124,8 @@
     default:
       emitWord(getBinaryCodeForInstr(*I));
       break;
-    case PPC::IMPLICIT_DEF:
+    case PPC::IMPLICIT_DEF_GPR:
+    case PPC::IMPLICIT_DEF_FP:
       break; // pseudo opcode, no side effects
     case PPC::MovePCtoLR:
       assert(0 && "CodeEmitter does not support MovePCtoLR instruction");


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.23 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.24
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.23	Wed Aug 24 17:45:17 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Wed Aug 24 18:08:16 2005
@@ -469,7 +469,6 @@
     std::cerr << "\n";
     abort();
   case ISD::EntryToken:       // These leaves remain the same.
-  case ISD::UNDEF:
     return Op;
   case ISD::TokenFactor: {
     SDOperand New;
@@ -525,6 +524,12 @@
     }
     break;
   }
+  case ISD::UNDEF:
+    if (N->getValueType(0) == MVT::i32)
+      CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR);
+    else
+      CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP);
+    break;
   case ISD::GlobalAddress: {
     GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
     SDOperand Tmp;


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.162 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.163
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.162	Wed Aug 24 17:21:47 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Aug 24 18:08:16 2005
@@ -830,7 +830,10 @@
     Node->dump(); std::cerr << '\n';
     assert(0 && "Node not handled!\n");
   case ISD::UNDEF:
-    BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
+    if (Node->getValueType(0) == MVT::i32)
+      BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Result);
+    else
+      BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Result);
     return Result;
   case ISD::DYNAMIC_STACKALLOC:
     // Generate both result values.  FIXME: Need a better commment here?
@@ -1872,8 +1875,11 @@
     return;
   case ISD::ImplicitDef:
     Select(N.getOperand(0));
-    BuildMI(BB, PPC::IMPLICIT_DEF, 0,
-            cast<RegisterSDNode>(N.getOperand(1))->getReg());
+    Tmp1 = cast<RegisterSDNode>(N.getOperand(1))->getReg();
+    if (N.getOperand(1).getValueType() == MVT::i32)
+      BuildMI(BB, PPC::IMPLICIT_DEF_GPR, 0, Tmp1);
+    else
+      BuildMI(BB, PPC::IMPLICIT_DEF_FP, 0, Tmp1);
     return;
   case ISD::RET:
     switch (N.getNumOperands()) {


Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.12 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.13
--- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.12	Wed Jul 27 01:12:33 2005
+++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp	Wed Aug 24 18:08:16 2005
@@ -40,7 +40,8 @@
         // minor pessimization that saves us from having to worry about
         // keeping the offsets up to date later when we emit long branch glue.
         return 12;
-      case PPC::IMPLICIT_DEF: // no asm emitted
+      case PPC::IMPLICIT_DEF_GPR: // no asm emitted
+      case PPC::IMPLICIT_DEF_FP: // no asm emitted
         return 0;
       default:
         break;


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.79 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.80
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.79	Mon Aug 22 20:16:46 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Wed Aug 24 18:08:16 2005
@@ -64,7 +64,8 @@
 def ADJCALLSTACKDOWN : Pseudo<(ops u16imm), "; ADJCALLSTACKDOWN">;
 def ADJCALLSTACKUP : Pseudo<(ops u16imm), "; ADJCALLSTACKUP">;
 }
-def IMPLICIT_DEF : Pseudo<(ops variable_ops), "; IMPLICIT_DEF">;
+def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC">;
+def IMPLICIT_DEF_FP  : Pseudo<(ops FPRC:$rD), "; %rD = IMPLICIT_DEF_FP">;
 
 let Defs = [LR] in
   def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label">;