[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.5 -> 1.6
---
Log message:

Before implementing copyfromreg, we'll implement copytoreg correctly.
This gets us this for the previous testcase:

_test:
        lis r2, 0
        ori r3, r2, 65535
        blr

Note that we actually write to r3 (the return reg) correctly now :)



---
Diffs of the changes:  (+6 -2)

 ScheduleDAG.cpp |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.5 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.6
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.5	Fri Aug 19 15:45:43 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Fri Aug 19 15:50:53 2005
@@ -36,14 +36,16 @@
     MachineBasicBlock *BB;
     const TargetMachine &TM;
     const TargetInstrInfo &TII;
+    const MRegisterInfo &MRI;
     SSARegMap *RegMap;
     
     std::map<SDNode *, unsigned> EmittedOps;
   public:
     SimpleSched(SelectionDAG &D, MachineBasicBlock *bb)
       : DAG(D), BB(bb), TM(D.getTarget()), TII(*TM.getInstrInfo()),
-        RegMap(BB->getParent()->getSSARegMap()) {
+        MRI(*TM.getRegisterInfo()), RegMap(BB->getParent()->getSSARegMap()) {
       assert(&TII && "Target doesn't provide instr info?");
+      assert(&MRI && "Target doesn't provide register info?");
     }
     
     void Run() {
@@ -131,7 +133,9 @@
     case ISD::EntryToken: break;
     case ISD::CopyToReg: {
       unsigned Val = Emit(Op.getOperand(2));
-      // FIXME: DO THE COPY NOW.
+      MRI.copyRegToReg(*BB, BB->end(),
+                       cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
+                       RegMap->getRegClass(Val));
       break;
     }
     }