[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.55 -> 1.56
---
Log message:

a bugfix (up top) and a quick repair job: disable generation of dep.z
(which died about a week ago) so we're back to load-(2^n-1)-then-AND
sequences. slow, but things should now be Almost Completely Working,
modulo those pesky alignment/ABI issues.



---
Diffs of the changes:  (+3 -3)

 IA64ISelPattern.cpp |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.55 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.56
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.55	Tue Aug 16 16:56:37 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Fri Aug 19 08:25:50 2005
@@ -1220,7 +1220,7 @@
     case MVT::i16: depositPos=0; depositLen=16; break;
     case MVT::i32: depositPos=0; depositLen=32; break;
     }
-    BuildMI(BB, IA64::DEPZ, 1, Result).addReg(Tmp1)
+    BuildMI(BB, IA64::DEPZ, 3, Result).addReg(Tmp1)
       .addImm(depositPos).addImm(depositLen);
     return Result;
   }
@@ -1439,7 +1439,7 @@
     case MVT::i32:
     case MVT::i64: {
       Tmp1 = SelectExpr(N.getOperand(0));
-      switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
+/* FIXME     switch (ponderIntegerAndWith(N.getOperand(1), Tmp3)) {
         case 1: // ANDing a constant that is 2^n-1 for some n
           switch (Tmp3) {
             case 8:  // if AND 0x00000000000000FF, be quaint and use zxt1
@@ -1457,7 +1457,7 @@
               break;
           }
           return Result; // early exit
-      } // fallthrough and emit a simple AND:
+  FIXME } */ // fallthrough and emit a simple AND:
       Tmp2 = SelectExpr(N.getOperand(1));
       BuildMI(BB, IA64::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }