[llvm-commits] CVS: llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp SchedGraph.cpp SchedGraphCommon.cpp SchedPriorities.cpp

Jeff Cohen jeffc at jolt-lang.org
Tue Jul 26 23:12:58 PDT 2005



Changes in directory llvm/lib/Target/SparcV9/InstrSched:

InstrScheduling.cpp updated: 1.84 -> 1.85
SchedGraph.cpp updated: 1.70 -> 1.71
SchedGraphCommon.cpp updated: 1.10 -> 1.11
SchedPriorities.cpp updated: 1.38 -> 1.39
---
Log message:

Eliminate all remaining tabs and trailing spaces.

---
Diffs of the changes:  (+20 -20)

 InstrScheduling.cpp  |   26 +++++++++++++-------------
 SchedGraph.cpp       |    8 ++++----
 SchedGraphCommon.cpp |    4 ++--
 SchedPriorities.cpp  |    2 +-
 4 files changed, 20 insertions(+), 20 deletions(-)


Index: llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.84 llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.85
--- llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp:1.84	Wed Jul 27 00:53:43 2005
+++ llvm/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp	Wed Jul 27 01:12:34 2005
@@ -672,14 +672,14 @@
         && ! S.schedPrio.nodeIsReady(*SI))
     {
       // successor not scheduled and not marked ready; check *its* preds.
-        
+
       bool succIsReady = true;
       for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P)
         if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) {
           succIsReady = false;
           break;
         }
-        
+
       if (succIsReady)  // add the successor to the ready list
         S.schedPrio.insertReady(*SI);
     }
@@ -828,7 +828,7 @@
           S.addChoiceToSlot(s, S.getChoice(i));
           noSlotFound = false;
         }
-        
+
       // No slot before `delayedNodeSlot' was found for this opCode
       // Use a later slot, and allow some delay slots to fall in
       // the next cycle.
@@ -838,9 +838,9 @@
             S.addChoiceToSlot(s, S.getChoice(i));
             break;
           }
-        
+
       assert(s < S.nslots && "No feasible slot for instruction?");
-        
+
       highestSlotUsed = std::max(highestSlotUsed, (int) s);
     }
 
@@ -867,7 +867,7 @@
     const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode);
     unsigned breakingSlot = INT_MAX;
     unsigned int nslotsToUse = S.nslots;
-        
+
     // Find the last possible slot for this instruction.
     for (int s = S.nslots-1; s >= (int) startSlot; s--)
       if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
@@ -884,7 +884,7 @@
          i < S.getNumChoices() && i < indexForBreakingNode; i++)
     {
       MachineOpCode opCode =S.getChoice(i)->getOpcode();
-        
+
       // If a higher priority instruction cannot be assigned to
       // any earlier slots, don't schedule the breaking instruction.
       //
@@ -896,10 +896,10 @@
             foundLowerSlot = true;
             nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
           }
-                
+
           S.addChoiceToSlot(s, S.getChoice(i));
         }
-        
+
       if (!foundLowerSlot)
         breakingSlot = INT_MAX;         // disable breaking instr
     }
@@ -912,7 +912,7 @@
       nslotsToUse = breakingSlot;
     } else
       nslotsToUse = S.nslots;
-        
+
     // For lower priority instructions than the one that breaks the
     // group, only assign them to slots lower than the breaking slot.
     // Otherwise, just ignore the instruction.
@@ -1198,7 +1198,7 @@
         sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
       else {
         nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
-        
+
         //remove the MI from the Machine Code For Instruction
         const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
         MachineCodeForInstruction& llvmMvec =
@@ -1350,7 +1350,7 @@
           nextTime++;
         }
       } while (S.isched.getInstr(nextSlot, nextTime) != NULL);
-        
+
       S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime);
       break;
     }
@@ -1457,7 +1457,7 @@
 
 bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
 {
-  SchedGraphSet graphSet(&F, target);   
+  SchedGraphSet graphSet(&F, target);
 
   if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
       std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";


Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp
diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.70 llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.71
--- llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp:1.70	Wed Jul 27 00:53:43 2005
+++ llvm/lib/Target/SparcV9/InstrSched/SchedGraph.cpp	Wed Jul 27 01:12:34 2005
@@ -365,7 +365,7 @@
               new SchedGraphEdge(prevNode, node, regNum,
                                  SchedGraphEdge::AntiDep);
           }
-        
+
           if (prevIsDef)
             if (!isDef || isDefAndUse)
               new SchedGraphEdge(prevNode, node, regNum,
@@ -646,7 +646,7 @@
   this->addMachineRegEdges(regToRefVecMap, target);
 
   // Finally, add edges from the dummy root and to dummy leaf
-  this->addDummyEdges();                
+  this->addDummyEdges();
 }
 
 
@@ -691,13 +691,13 @@
      << sink->getNodeId() << "] : ";
 
   switch(depType) {
-  case SchedGraphEdge::CtrlDep:         
+  case SchedGraphEdge::CtrlDep:
     os<< "Control Dep";
     break;
   case SchedGraphEdge::ValueDep:
     os<< "Reg Value " << *val;
     break;
-  case SchedGraphEdge::MemoryDep:       
+  case SchedGraphEdge::MemoryDep:
     os<< "Memory Dep";
     break;
   case SchedGraphEdge::MachineRegister:


Index: llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp
diff -u llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.10 llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.11
--- llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp:1.10	Wed Jul 27 00:53:43 2005
+++ llvm/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp	Wed Jul 27 01:12:34 2005
@@ -173,8 +173,8 @@
 
 void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node,
                                           bool addDummyEdges) {
-  this->eraseIncomingEdges(node, addDummyEdges);        
-  this->eraseOutgoingEdges(node, addDummyEdges);        
+  this->eraseIncomingEdges(node, addDummyEdges);
+  this->eraseOutgoingEdges(node, addDummyEdges);
 }
 
 } // End llvm namespace


Index: llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp
diff -u llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.38 llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.39
--- llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp:1.38	Wed Jul 27 00:53:43 2005
+++ llvm/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp	Wed Jul 27 01:12:34 2005
@@ -173,7 +173,7 @@
 inline int
 SchedPriorities::chooseByRule3(std::vector<candIndex>& mcands) {
   assert(mcands.size() >= 1 && "Should have at least one candidate here.");
-  int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges();       
+  int maxUses = candsAsHeap.getNode(mcands[0])->getNumOutEdges();
   int indexWithMaxUses = 0;
   for (unsigned i=1, N = mcands.size(); i < N; i++) {
     int numUses = candsAsHeap.getNode(mcands[i])->getNumOutEdges();






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