[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp AlphaInstrInfo.td AlphaRegisterInfo.td
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Tue Jun 28 17:31:20 PDT 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.136 -> 1.137
AlphaInstrInfo.td updated: 1.48 -> 1.49
AlphaRegisterInfo.td updated: 1.10 -> 1.11
---
Log message:
Get rid of all symbolic loads. I now do gernate all relocations sequences
rather than relying on the assembler. Only a few more pseudo instructions
left. Also merge load code paths.
---
Diffs of the changes: (+76 -230)
AlphaISelPattern.cpp | 265 ++++++++++++---------------------------------------
AlphaInstrInfo.td | 33 ------
AlphaRegisterInfo.td | 8 +
3 files changed, 76 insertions(+), 230 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.136 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.137
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.136 Mon Jun 27 18:24:11 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Tue Jun 28 19:31:08 2005
@@ -92,9 +92,10 @@
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
- setOperationAction(ISD::ZEXTLOAD, MVT::i1 , Expand);
- setOperationAction(ISD::ZEXTLOAD, MVT::i32 , Expand);
+ setOperationAction(ISD::ZEXTLOAD, MVT::i1, Expand);
+ setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
@@ -844,26 +845,6 @@
return l - h * IMM_MULT;
}
-static unsigned GetSymVersion(unsigned opcode)
-{
- switch (opcode) {
- default: assert(0 && "unknown load or store"); return 0;
- case Alpha::LDQ: return Alpha::LDQ_SYM;
- case Alpha::LDS: return Alpha::LDS_SYM;
- case Alpha::LDT: return Alpha::LDT_SYM;
- case Alpha::LDL: return Alpha::LDL_SYM;
- case Alpha::LDBU: return Alpha::LDBU_SYM;
- case Alpha::LDWU: return Alpha::LDWU_SYM;
- case Alpha::LDW: return Alpha::LDW_SYM;
- case Alpha::LDB: return Alpha::LDB_SYM;
- case Alpha::STQ: return Alpha::STQ_SYM;
- case Alpha::STS: return Alpha::STS_SYM;
- case Alpha::STT: return Alpha::STT_SYM;
- case Alpha::STL: return Alpha::STL_SYM;
- case Alpha::STW: return Alpha::STW_SYM;
- case Alpha::STB: return Alpha::STB_SYM;
- }
-}
static unsigned GetRelVersion(unsigned opcode)
{
switch (opcode) {
@@ -1212,74 +1193,6 @@
BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
return Result;
- case ISD::CopyFromReg:
- {
- // Make sure we generate both values.
- if (Result != notIn)
- ExprMap[N.getValue(1)] = notIn; // Generate the token
- else
- Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
- SDOperand Chain = N.getOperand(0);
-
- Select(Chain);
- unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
- //std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
- BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
- return Result;
- }
-
- case ISD::LOAD:
- {
- // Make sure we generate both values.
- if (Result != notIn)
- ExprMap[N.getValue(1)] = notIn; // Generate the token
- else
- Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
- DestType = N.getValue(0).getValueType();
-
- SDOperand Chain = N.getOperand(0);
- SDOperand Address = N.getOperand(1);
- Select(Chain);
- Opc = DestType == MVT::f64 ? Alpha::LDT : Alpha::LDS;
-
- if (EnableAlphaLSMark)
- {
- int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
- ->getValue());
- int j = getFunctionOffset(BB->getParent()->getFunction());
- BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
- }
-
- if (Address.getOpcode() == ISD::GlobalAddress) {
- AlphaLowering.restoreGP(BB);
- Opc = GetSymVersion(Opc);
- has_sym = true;
- BuildMI(BB, Opc, 1, Result)
- .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
- }
- else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
- AlphaLowering.restoreGP(BB);
- Opc = GetRelVersion(Opc);
- has_sym = true;
- Tmp1 = MakeReg(MVT::i64);
- BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
- .addReg(Alpha::R29);
- BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
- .addReg(Tmp1);
- }
- else if(Address.getOpcode() == ISD::FrameIndex) {
- BuildMI(BB, Opc, 2, Result)
- .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
- .addReg(Alpha::F31);
- } else {
- long offset;
- SelectAddr(Address, Tmp1, offset);
- BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
- }
- return Result;
- }
case ISD::ConstantFP:
if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N)) {
if (CN->isExactlyValue(+0.0)) {
@@ -1323,63 +1236,6 @@
}
return Result;
- case ISD::EXTLOAD:
- {
- //include a conversion sequence for float loads to double
- if (Result != notIn)
- ExprMap[N.getValue(1)] = notIn; // Generate the token
- else
- Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
- Tmp1 = MakeReg(MVT::f32);
-
- assert(cast<MVTSDNode>(Node)->getExtraValueType() == MVT::f32 &&
- "EXTLOAD not from f32");
- assert(Node->getValueType(0) == MVT::f64 && "EXTLOAD not to f64");
-
- SDOperand Chain = N.getOperand(0);
- SDOperand Address = N.getOperand(1);
- Select(Chain);
-
- if (EnableAlphaLSMark)
- {
- int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
- ->getValue());
- int j = getFunctionOffset(BB->getParent()->getFunction());
- BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
- }
-
- if (Address.getOpcode() == ISD::GlobalAddress) {
- AlphaLowering.restoreGP(BB);
- has_sym = true;
- BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1)
- .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
- }
- else if (ConstantPoolSDNode *CP =
- dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
- {
- AlphaLowering.restoreGP(BB);
- has_sym = true;
- Tmp2 = MakeReg(MVT::i64);
- BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(CP->getIndex())
- .addReg(Alpha::R29);
- BuildMI(BB, Alpha::LDSr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
- .addReg(Tmp2);
- }
- else if(Address.getOpcode() == ISD::FrameIndex) {
- Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
- BuildMI(BB, Alpha::LDS, 2, Tmp1)
- .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
- .addReg(Alpha::F31);
- } else {
- long offset;
- SelectAddr(Address, Tmp2, offset);
- BuildMI(BB, Alpha::LDS, 1, Tmp1).addImm(offset).addReg(Tmp2);
- }
- BuildMI(BB, Alpha::CVTST, 1, Result).addReg(Tmp1);
- return Result;
- }
-
case ISD::SINT_TO_FP:
{
assert (N.getOperand(0).getValueType() == MVT::i64
@@ -1425,17 +1281,10 @@
}
}
- if ((DestType == MVT::f64 || DestType == MVT::f32 ||
- (
- (opcode == ISD::LOAD || opcode == ISD::CopyFromReg ||
- opcode == ISD::EXTLOAD) &&
- (N.getValue(0).getValueType() == MVT::f32 ||
- N.getValue(0).getValueType() == MVT::f64)
- ))
- && opcode != ISD::CALL && opcode != ISD::TAILCALL
- )
+ if ((DestType == MVT::f64 || DestType == MVT::f32)
+ && opcode != ISD::CALL && opcode != ISD::TAILCALL)
return SelectExprFP(N, Result);
-
+
switch (opcode) {
default:
Node->dump();
@@ -1550,10 +1399,15 @@
SDOperand Address = N.getOperand(1);
Select(Chain);
- assert(Node->getValueType(0) == MVT::i64 &&
- "Unknown type to sign extend to.");
+ bool fpext = true;
+
if (opcode == ISD::LOAD)
- Opc = Alpha::LDQ;
+ switch (Node->getValueType(0)) {
+ default: Node->dump(); assert(0 && "Bad load!");
+ case MVT::i64: Opc = Alpha::LDQ; break;
+ case MVT::f64: Opc = Alpha::LDT; break;
+ case MVT::f32: Opc = Alpha::LDS; break;
+ }
else
switch (cast<MVTSDNode>(Node)->getExtraValueType()) {
default: Node->dump(); assert(0 && "Bad sign extend!");
@@ -1566,38 +1420,50 @@
assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
}
- if (EnableAlphaLSMark)
- {
- int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
- ->getValue());
- int j = getFunctionOffset(BB->getParent()->getFunction());
- BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ int i = 0, j = 0;
+ if (EnableAlphaLSMark) {
+ i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))
+ ->getValue());
+ j = getFunctionOffset(BB->getParent()->getFunction());
}
-
- if (Address.getOpcode() == ISD::GlobalAddress) {
- AlphaLowering.restoreGP(BB);
- Opc = GetSymVersion(Opc);
- has_sym = true;
- BuildMI(BB, Opc, 1, Result)
- .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
- }
- else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
+ if (GlobalAddressSDNode *GASD =
+ dyn_cast<GlobalAddressSDNode>(Address)) {
+ if (GASD->getGlobal()->isExternal()) {
+ Tmp1 = SelectExpr(Address);
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ BuildMI(BB, Opc, 2, Result).addImm(0).addReg(Tmp1);
+ } else {
+ Tmp1 = MakeReg(MVT::i64);
+ AlphaLowering.restoreGP(BB);
+ BuildMI(BB, Alpha::LDAHr, 2, Tmp1)
+ .addGlobalAddress(GASD->getGlobal()).addReg(Alpha::R29);
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ BuildMI(BB, GetRelVersion(Opc), 2, Result)
+ .addGlobalAddress(GASD->getGlobal()).addReg(Tmp1);
+ }
+ } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
AlphaLowering.restoreGP(BB);
- Opc = GetRelVersion(Opc);
has_sym = true;
Tmp1 = MakeReg(MVT::i64);
BuildMI(BB, Alpha::LDAHr, 2, Tmp1).addConstantPoolIndex(CP->getIndex())
.addReg(Alpha::R29);
- BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CP->getIndex())
- .addReg(Tmp1);
- }
- else if(Address.getOpcode() == ISD::FrameIndex) {
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ BuildMI(BB, GetRelVersion(Opc), 2, Result)
+ .addConstantPoolIndex(CP->getIndex()).addReg(Tmp1);
+ } else if(Address.getOpcode() == ISD::FrameIndex) {
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, Opc, 2, Result)
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
.addReg(Alpha::F31);
} else {
long offset;
SelectAddr(Address, Tmp1, offset);
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, Opc, 2, Result).addImm(offset).addReg(Tmp1);
}
return Result;
@@ -1606,7 +1472,11 @@
case ISD::GlobalAddress:
AlphaLowering.restoreGP(BB);
has_sym = true;
- BuildMI(BB, Alpha::LDQrl, 2, Result)
+
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(0).addImm(0).addImm(getUID());
+
+ BuildMI(BB, Alpha::LDQl, 2, Result)
.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal())
.addReg(Alpha::R29);
return Result;
@@ -1922,7 +1792,10 @@
Select(Chain);
unsigned r = dyn_cast<RegSDNode>(Node)->getReg();
//std::cerr << "CopyFromReg " << Result << " = " << r << "\n";
- BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
+ if (DestType == MVT::f32 || DestType == MVT::f64)
+ BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r);
+ else
+ BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r);
return Result;
}
@@ -2422,32 +2295,24 @@
}
}
- if (EnableAlphaLSMark)
- {
- int i =
+ int i = 0, j = 0;
+ if (EnableAlphaLSMark) {
+ i =
getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
- int j = getFunctionOffset(BB->getParent()->getFunction());
- BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ j = getFunctionOffset(BB->getParent()->getFunction());
}
- if (Address.getOpcode() == ISD::GlobalAddress)
- {
- AlphaLowering.restoreGP(BB);
- Opc = GetSymVersion(Opc);
- has_sym = true;
- BuildMI(BB, Opc, 2).addReg(Tmp1)
- .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
- }
- else if(Address.getOpcode() == ISD::FrameIndex)
- {
+ if(Address.getOpcode() == ISD::FrameIndex) {
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, Opc, 3).addReg(Tmp1)
.addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
.addReg(Alpha::F31);
- }
- else
- {
+ } else {
long offset;
SelectAddr(Address, Tmp2, offset);
+ if (EnableAlphaLSMark)
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
}
return;
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.48 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.49
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.48 Mon Jun 27 16:11:40 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Tue Jun 28 19:31:08 2005
@@ -53,30 +53,6 @@
Uses = [R29] in
def CALL : PseudoInstAlpha< (ops s64imm:$TARGET), "jsr $TARGET">; //Jump to subroutine
-//These are evil as they get expanded into multiple instructions to take care of reallocation
-let Uses = [R29], Defs = [R28] in {
- def LDQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldq $RA,$DISP">; //Load quadword
- def LDS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "lds $RA,$DISP">; //Load float
- def LDT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "ldt $RA,$DISP">; //Load double
- def LDL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldl $RA,$DISP">; // Load sign-extended longword
- def LDBU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldbu $RA,$DISP">; //Load zero-extended byte
- def LDWU_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldwu $RA,$DISP">; //Load zero-extended word
- def LDW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldw $RA,$DISP">; // Load sign-extended word
- def LDB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "ldb $RA,$DISP">; //Load byte
-
- def LDW : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldw $RA,$DISP($RB)">; // Load sign-extended word
- def LDB : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldb $RA,$DISP($RB)">; //Load byte
-
- def STB_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stb $RA,$DISP">; // Store byte
- def STW_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stw $RA,$DISP">; // Store word
- def STL_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stl $RA,$DISP">; // Store longword
- def STQ_SYM : PseudoInstAlpha<(ops GPRC:$RA, s16imm:$DISP), "stq $RA,$DISP">; //Store quadword
-
- def STS_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "sts $RA,$DISP">; //store float
- def STT_SYM : PseudoInstAlpha<(ops GPRC:$RA, s64imm:$DISP), "stt $RA,$DISP">; //store double
-}
-
-
//RESULTS of these go to R27
//These are also evil as the assembler expands them into calls
let Uses = [R29],
@@ -357,21 +333,22 @@
def LDAH : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB)">; //Load address high
-//Loads, int, Rellocated form
+//Loads, int, Rellocated Low form
def LDLr : MForm<0x28, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldl $RA,$DISP($RB) !gprellow">; // Load sign-extended longword
def LDQr : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !gprellow">; //Load quadword
def LDBUr : MForm<0x0A, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldbu $RA,$DISP($RB) !gprellow">; //Load zero-extended byte
def LDWUr : MForm<0x0C, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldwu $RA,$DISP($RB) !gprellow">; //Load zero-extended word
-def LDQrl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
-//Loads, float, Rellocated form
+//Loads, float, Rellocated Low form
def LDSr : MForm<0x22, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "lds $RA,$DISP($RB) !gprellow">; //Load S_floating
def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) !gprellow">; //Load T_floating
-//Load address, rellocated form
+//Load address, rellocated low and high form
def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) !gprellow">; //Load address
def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">; //Load address high
+//Load quad, rellocated literal form
+def LDQl : MForm<0x29, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldq $RA,$DISP($RB) !literal">; //Load quadword
//Branches, int
def BEQ : BForm<0x39, (ops GPRC:$RA, s21imm:$DISP), "beq $RA,$DISP">; //Branch if = zero
Index: llvm/lib/Target/Alpha/AlphaRegisterInfo.td
diff -u llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.10 llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.11
--- llvm/lib/Target/Alpha/AlphaRegisterInfo.td:1.10 Mon Jun 27 10:36:48 2005
+++ llvm/lib/Target/Alpha/AlphaRegisterInfo.td Tue Jun 28 19:31:08 2005
@@ -82,9 +82,13 @@
def GPRC : RegisterClass<i64, 64,
// Volatile
[R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22,
- R23, R24, R25, R26, R27,
+ R23, R24, R25,
+ //Special meaning, but volatile
+ R27, //procedure address
+ R26, //return address
+ R29, //global offset table address
// Non-volatile
- R9, R10, R11, R12, R13, R14, R29 ]>;
+ R9, R10, R11, R12, R13, R14 ]>;
// Note: R28 is reserved for the assembler
// Don't allocate 15, 29, 30, 31
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