[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC64ISelPattern.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.80 -> 1.81
PPC64ISelPattern.cpp updated: 1.12 -> 1.13
---
Log message:

Implement count leading zeros (ctlz), count trailing zeros (cttz), and count
population (ctpop).  Generic lowering is implemented, however only promotion 
is implemented for SelectionDAG at the moment.

More coming soon.



---
Diffs of the changes:  (+10 -0)

 PPC32ISelPattern.cpp |    5 +++++
 PPC64ISelPattern.cpp |    5 +++++
 2 files changed, 10 insertions(+)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.80 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.81
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.80	Fri Apr 29 23:26:06 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue May  3 12:19:29 2005
@@ -69,6 +69,11 @@
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
       setOperationAction(ISD::FSQRT, MVT::f32, Expand);
 
+      //PowerPC has these, but they are not implemented
+      setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
+      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+      setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
+
       setSetCCResultContents(ZeroOrOneSetCCResult);
       addLegalFPImmediate(+0.0); // Necessary for FSEL
       addLegalFPImmediate(-0.0); //


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.12 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.13
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.12	Fri Apr 29 23:26:56 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Tue May  3 12:19:29 2005
@@ -68,6 +68,11 @@
       setOperationAction(ISD::SREM, MVT::i64, Expand);
       setOperationAction(ISD::UREM, MVT::i64, Expand);
 
+      // PowerPC has these, but they are not implemented
+      setOperationAction(ISD::CTPOP, MVT::i64, Expand);
+      setOperationAction(ISD::CTTZ , MVT::i64, Expand);
+      setOperationAction(ISD::CTTZ , MVT::i64, Expand);
+
       setShiftAmountFlavor(Extend);   // shl X, 32 == 0
       addLegalFPImmediate(+0.0); // Necessary for FSEL
       addLegalFPImmediate(-0.0); //