[llvm-commits] CVS: llvm/lib/Target/SparcV8/DelaySlotFiller.cpp FPMover.cpp SparcV8.h SparcV8AsmPrinter.cpp SparcV8CodeEmitter.cpp SparcV8ISelSimple.cpp SparcV8InstrInfo.cpp SparcV8InstrInfo.h SparcV8JITInfo.h SparcV8RegisterInfo.cpp SparcV8RegisterInfo.h SparcV8TargetMachine.cpp SparcV8TargetMachine.h

Misha Brukman brukman at cs.uiuc.edu
Thu Apr 21 16:21:41 PDT 2005



Changes in directory llvm/lib/Target/SparcV8:

DelaySlotFiller.cpp updated: 1.8 -> 1.9
FPMover.cpp updated: 1.3 -> 1.4
SparcV8.h updated: 1.5 -> 1.6
SparcV8AsmPrinter.cpp updated: 1.31 -> 1.32
SparcV8CodeEmitter.cpp updated: 1.3 -> 1.4
SparcV8ISelSimple.cpp updated: 1.89 -> 1.90
SparcV8InstrInfo.cpp updated: 1.7 -> 1.8
SparcV8InstrInfo.h updated: 1.4 -> 1.5
SparcV8JITInfo.h updated: 1.1 -> 1.2
SparcV8RegisterInfo.cpp updated: 1.24 -> 1.25
SparcV8RegisterInfo.h updated: 1.4 -> 1.5
SparcV8TargetMachine.cpp updated: 1.25 -> 1.26
SparcV8TargetMachine.h updated: 1.4 -> 1.5
---
Log message:

Remove trailing whitespace


---
Diffs of the changes:  (+83 -83)

 DelaySlotFiller.cpp      |    4 +-
 FPMover.cpp              |    4 +-
 SparcV8.h                |    4 +-
 SparcV8AsmPrinter.cpp    |   26 +++++++++----------
 SparcV8CodeEmitter.cpp   |    8 ++---
 SparcV8ISelSimple.cpp    |   64 +++++++++++++++++++++++------------------------
 SparcV8InstrInfo.cpp     |    4 +-
 SparcV8InstrInfo.h       |    4 +-
 SparcV8JITInfo.h         |    8 ++---
 SparcV8RegisterInfo.cpp  |   10 +++----
 SparcV8RegisterInfo.h    |    6 ++--
 SparcV8TargetMachine.cpp |   16 +++++------
 SparcV8TargetMachine.h   |    8 ++---
 13 files changed, 83 insertions(+), 83 deletions(-)


Index: llvm/lib/Target/SparcV8/DelaySlotFiller.cpp
diff -u llvm/lib/Target/SparcV8/DelaySlotFiller.cpp:1.8 llvm/lib/Target/SparcV8/DelaySlotFiller.cpp:1.9
--- llvm/lib/Target/SparcV8/DelaySlotFiller.cpp:1.8	Wed Sep 29 23:04:47 2004
+++ llvm/lib/Target/SparcV8/DelaySlotFiller.cpp	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===-- DelaySlotFiller.cpp - SparcV8 delay slot filler -------------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This is a simple local pass that fills delay slots with NOPs.


Index: llvm/lib/Target/SparcV8/FPMover.cpp
diff -u llvm/lib/Target/SparcV8/FPMover.cpp:1.3 llvm/lib/Target/SparcV8/FPMover.cpp:1.4
--- llvm/lib/Target/SparcV8/FPMover.cpp:1.3	Thu Dec  9 22:42:45 2004
+++ llvm/lib/Target/SparcV8/FPMover.cpp	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===-- FPMover.cpp - SparcV8 double-precision floating point move fixer --===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // Turns FpMOVD instructions into FMOVS pairs after regalloc.


Index: llvm/lib/Target/SparcV8/SparcV8.h
diff -u llvm/lib/Target/SparcV8/SparcV8.h:1.5 llvm/lib/Target/SparcV8/SparcV8.h:1.6
--- llvm/lib/Target/SparcV8/SparcV8.h:1.5	Tue Sep 28 22:25:39 2004
+++ llvm/lib/Target/SparcV8/SparcV8.h	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the entry points for global functions defined in the LLVM


Index: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.31 llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.32
--- llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.31	Mon Mar 14 22:54:20 2005
+++ llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===-- SparcV8AsmPrinter.cpp - SparcV8 LLVM assembly writer --------------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains a printer that converts from our internal representation
@@ -71,7 +71,7 @@
     void printOperand(const MachineInstr *MI, int opNum);
     void printBaseOffsetPair (const MachineInstr *MI, int i, bool brackets=true);
     void printMachineInstruction(const MachineInstr *MI);
-    bool runOnMachineFunction(MachineFunction &F);    
+    bool runOnMachineFunction(MachineFunction &F);
     bool doInitialization(Module &M);
     bool doFinalization(Module &M);
   };
@@ -203,7 +203,7 @@
 
 // Print a constant value or values, with the appropriate storage class as a
 // prefix.
-void V8Printer::emitGlobalConstant(const Constant *CV) {  
+void V8Printer::emitGlobalConstant(const Constant *CV) {
   const TargetData &TD = TM.getTargetData();
 
   if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV)) {
@@ -235,7 +235,7 @@
 
       // Insert the field padding unless it's zero bytes...
       if (padSize)
-        O << "\t.skip\t " << padSize << "\n";      
+        O << "\t.skip\t " << padSize << "\n";
     }
     assert(sizeSoFar == cvsLayout->StructSize &&
            "Layout of constant struct may be incorrect!");
@@ -268,7 +268,7 @@
     }
   } else if (isa<UndefValue> (CV)) {
     unsigned size = TD.getTypeSize (CV->getType ());
-    O << "\t.skip\t " << size << "\n";      
+    O << "\t.skip\t " << size << "\n";
     return;
   } else if (isa<ConstantAggregateZero> (CV)) {
     unsigned size = TD.getTypeSize (CV->getType ());
@@ -311,7 +311,7 @@
 void V8Printer::printConstantPool(MachineConstantPool *MCP) {
   const std::vector<Constant*> &CP = MCP->getConstants();
   const TargetData &TD = TM.getTargetData();
- 
+
   if (CP.empty()) return;
 
   for (unsigned i = 0, e = CP.size(); i != e; ++i) {
@@ -424,7 +424,7 @@
     O << ".CPI" << CurrentFnName << "_" << MO.getConstantPoolIndex();
     break;
   default:
-    O << "<unknown operand type>"; abort (); break;    
+    O << "<unknown operand type>"; abort (); break;
   }
   if (CloseParen) O << ")";
 }
@@ -511,7 +511,7 @@
     O << "! ";
 
   O << Desc.Name << " ";
-  
+
   // Printing memory instructions is a special case.
   // for loads:  %dest = op %base, offset --> op [%base + offset], %dest
   // for stores: op %base, offset, %src   --> op %src, [%base + offset]
@@ -550,7 +550,7 @@
   for (unsigned i = 0; i < MI->getNumOperands (); ++i)
     if (MI->getOperand (i).isRegister () && MI->getOperand (i).isDef ())
       print_order.push_back (i);
-  for (unsigned i = 0, e = print_order.size (); i != e; ++i) { 
+  for (unsigned i = 0, e = print_order.size (); i != e; ++i) {
     printOperand (MI, print_order[i]);
     if (i != (print_order.size () - 1))
       O << ", ";
@@ -588,13 +588,13 @@
       unsigned Size = TD.getTypeSize(C->getType());
       unsigned Align = TD.getTypeAlignment(C->getType());
 
-      if (C->isNullValue() && 
+      if (C->isNullValue() &&
           (I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
            I->hasWeakLinkage() /* FIXME: Verify correct */)) {
         SwitchSection(O, CurSection, ".data");
         if (I->hasInternalLinkage())
           O << "\t.local " << name << "\n";
-        
+
         O << "\t.comm " << name << "," << TD.getTypeSize(C->getType())
           << "," << (unsigned)TD.getTypeAlignment(C->getType());
         O << "\t\t! ";
@@ -609,7 +609,7 @@
           SwitchSection(O, CurSection, "");
           O << "\t.section\t\".llvm.linkonce.d." << name << "\",\"aw\", at progbits\n";
           break;
-        
+
         case GlobalValue::AppendingLinkage:
           // FIXME: appending linkage variables should go into a section of
           // their name or something.  For now, just emit them as external.


Index: llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp:1.3 llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp:1.4
--- llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp:1.3	Fri Dec  3 00:57:14 2004
+++ llvm/lib/Target/SparcV8/SparcV8CodeEmitter.cpp	Thu Apr 21 18:21:30 2005
@@ -1,12 +1,12 @@
 //===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 //
 //===----------------------------------------------------------------------===//
 
@@ -78,7 +78,7 @@
                                                       MachineCodeEmitter &MCE) {
   // Keep as `true' until this is a functional JIT to allow llvm-gcc to build
   return true;
-  
+
   // Machine code emitter pass for SparcV8
   PM.add(new SparcV8CodeEmitter(*this, MCE));
   // Delete machine code for this function after emitting it


Index: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.89 llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.90
--- llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.89	Mon Mar 14 22:54:20 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file defines a simple peephole instruction selector for the V8 target
@@ -318,7 +318,7 @@
     BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
   } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
     // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
-    // that SETHI %reg,global == SETHI %reg,%hi(global) and 
+    // that SETHI %reg,global == SETHI %reg,%hi(global) and
     // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
     unsigned TmpReg = makeAnotherReg (C->getType ());
     BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress(GV);
@@ -362,10 +362,10 @@
   const unsigned *IAR = &IncomingArgRegs[0];
   unsigned ArgOffset = 68;
 
-  // Store registers onto stack if this is a varargs function. 
+  // Store registers onto stack if this is a varargs function.
   // FIXME: This doesn't really pertain to "loading arguments into
   // virtual registers", so it's not clear that it really belongs here.
-  // FIXME: We could avoid storing any args onto the stack that don't 
+  // FIXME: We could avoid storing any args onto the stack that don't
   // need to be in memory, because they come before the ellipsis in the
   // parameter list (and thus could never be accessed through va_arg).
   if (LF->getFunctionType ()->isVarArg ()) {
@@ -505,7 +505,7 @@
             break;
           }
         assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
-        
+
         unsigned ValReg;
         std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
           PHIValues.lower_bound(PredMBB);
@@ -515,7 +515,7 @@
           // predecessor.  Recycle it.
           ValReg = EntryIt->second;
 
-        } else {        
+        } else {
           // Get the incoming value into a virtual register.
           //
           Value *Val = PN->getIncomingValue(i);
@@ -534,11 +534,11 @@
             // might be arbitrarily complex if it is a constant expression),
             // just insert the computation at the top of the basic block.
             MachineBasicBlock::iterator PI = PredMBB->begin();
-            
+
             // Skip over any PHI nodes though!
             while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
               ++PI;
-            
+
             ValReg = getReg(Val, PredMBB, PI);
           }
 
@@ -568,28 +568,28 @@
   // First pass over the function, lower any unknown intrinsic functions
   // with the IntrinsicLowering class.
   LowerUnknownIntrinsicFunctionCalls(Fn);
-  
+
   F = &MachineFunction::construct(&Fn, TM);
-  
+
   // Create all of the machine basic blocks for the function...
   for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
     F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
-  
+
   BB = &F->front();
-  
+
   // Set up a frame object for the return address.  This is used by the
   // llvm.returnaddress & llvm.frameaddress intrinisics.
   //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
-  
+
   // Copy incoming arguments off of the stack and out of fixed registers.
   LoadArgumentsToVirtualRegs(&Fn);
-  
+
   // Instruction select everything except PHI nodes
   visit(Fn);
-  
+
   // Select the PHI nodes
   SelectPHINodes();
-  
+
   RegMap.clear();
   MBBMap.clear();
   F = 0;
@@ -632,11 +632,11 @@
                                   const Type *newTy, unsigned DestReg) {
   unsigned FPCastOpcode, FPStoreOpcode, FPSize, FPAlign;
   unsigned oldTyClass = getClassB(oldTy);
-  if (oldTyClass == cFloat) { 
-    FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4; 
+  if (oldTyClass == cFloat) {
+    FPCastOpcode = V8::FSTOI; FPStoreOpcode = V8::STFri; FPSize = 4;
     FPAlign = TM.getTargetData().getFloatAlignment();
   } else { // it's a double
-    FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8; 
+    FPCastOpcode = V8::FDTOI; FPStoreOpcode = V8::STDFri; FPSize = 8;
     FPAlign = TM.getTargetData().getDoubleAlignment();
   }
   unsigned TempReg = makeAnotherReg (oldTy);
@@ -672,11 +672,11 @@
     case cShort:
     case cInt:
       switch (oldTyClass) {
-      case cLong: 
+      case cLong:
         // Treat it like a cast from the lower half of the value.
         emitIntegerCast (BB, IP, Type::IntTy, SrcReg+1, newTy, DestReg);
         break;
-      case cFloat: 
+      case cFloat:
       case cDouble:
         emitFPToIntegerCast (BB, IP, oldTy, SrcReg, newTy, DestReg);
         break;
@@ -742,10 +742,10 @@
         unsigned TempReg = emitIntegerCast (BB, IP, OldHalfTy, SrcReg,
                                             NewHalfTy, DestReg+1, true);
         if (newTy->isSigned ()) {
-          BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg) 
+          BuildMI (*BB, IP, V8::SRAri, 2, DestReg).addReg (TempReg)
             .addZImm (31);
         } else {
-          BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0) 
+          BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0)
             .addReg (V8::G0);
         }
         break;
@@ -1162,7 +1162,7 @@
       if (isa<ConstantIntegral> (idx)) {
         // If idx is a constant, we don't have to emit the multiply.
         int64_t Val = cast<ConstantIntegral> (idx)->getRawValue ();
-        if ((Val * elementSize) + 4096 < 8191) { 
+        if ((Val * elementSize) + 4096 < 8191) {
           // (Val * elementSize) is constant and fits in an immediate field.
           // emit: nextBasePtrReg = ADDri basePtrReg, (Val * elementSize)
           addImmed = true;
@@ -1180,16 +1180,16 @@
         OffsetReg = makeAnotherReg (Type::IntTy);
         unsigned idxReg = getReg (idx, MBB, IP);
         switch (elementSize) {
-          case 1: 
+          case 1:
             BuildMI (*MBB, IP, V8::ORrr, 2, OffsetReg).addReg (V8::G0).addReg (idxReg);
             break;
-          case 2: 
+          case 2:
             BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (1);
             break;
-          case 4: 
+          case 4:
             BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (2);
             break;
-          case 8: 
+          case 8:
             BuildMI (*MBB, IP, V8::SLLri, 2, OffsetReg).addReg (idxReg).addZImm (3);
             break;
           default: {
@@ -1343,7 +1343,7 @@
     //   ba .lshr_continue
 
     BB = oneShiftMBB;
-    
+
     if (isSigned)
       BuildMI (BB, V8::SRAri, 2, OneShiftOutReg).addReg (SrcReg).addZImm (31);
     else
@@ -1515,7 +1515,7 @@
   }
 
   switch (getClassB (I.getType ())) {
-    case cByte: 
+    case cByte:
       if (I.getType ()->isSigned ()) { // add byte
         BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
       } else { // add ubyte
@@ -1562,7 +1562,7 @@
   unsigned Op1Reg = getReg (I.getOperand (1));
   unsigned DestReg = getReg (I);
   const Type *Ty = I.getOperand (0)->getType ();
-  
+
   // Compare the two values.
   if (getClass (Ty) < cLong) {
     BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.7 llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.8
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp:1.7	Fri Dec 10 23:19:03 2004
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.cpp	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the TargetInstrInfo class.


Index: llvm/lib/Target/SparcV8/SparcV8InstrInfo.h
diff -u llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.4 llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.5
--- llvm/lib/Target/SparcV8/SparcV8InstrInfo.h:1.4	Sun Jul 25 01:19:04 2004
+++ llvm/lib/Target/SparcV8/SparcV8InstrInfo.h	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the TargetInstrInfo class.


Index: llvm/lib/Target/SparcV8/SparcV8JITInfo.h
diff -u llvm/lib/Target/SparcV8/SparcV8JITInfo.h:1.1 llvm/lib/Target/SparcV8/SparcV8JITInfo.h:1.2
--- llvm/lib/Target/SparcV8/SparcV8JITInfo.h:1.1	Wed Feb 25 13:28:19 2004
+++ llvm/lib/Target/SparcV8/SparcV8JITInfo.h	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the TargetJITInfo class.
@@ -30,14 +30,14 @@
     /// is not supported for this target.
     ///
     virtual void addPassesToJITCompile(FunctionPassManager &PM);
-    
+
     /// replaceMachineCodeForFunction - Make it so that calling the function
     /// whose machine code is at OLD turns into a call to NEW, perhaps by
     /// overwriting OLD with a branch to NEW.  This is used for self-modifying
     /// code.
     ///
     virtual void replaceMachineCodeForFunction(void *Old, void *New);
-    
+
     /// getJITStubForFunction - Create or return a stub for the specified
     /// function.  This stub acts just like the specified function, except that
     /// it allows the "address" of the function to be taken without having to


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.24 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.25
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp:1.24	Fri Oct 29 16:42:27 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.cpp	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the MRegisterInfo class.
@@ -44,7 +44,7 @@
   const TargetRegisterClass *RC = getClass(SrcReg);
 
   // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
-  if (RC == SparcV8::IntRegsRegisterClass) 
+  if (RC == SparcV8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
       .addReg (SrcReg);
   else if (RC == SparcV8::FPRegsRegisterClass)
@@ -61,7 +61,7 @@
 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                      unsigned DestReg, int FrameIdx) const {
   const TargetRegisterClass *RC = getClass(DestReg);
-  if (RC == SparcV8::IntRegsRegisterClass) 
+  if (RC == SparcV8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
   else if (RC == SparcV8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
@@ -77,7 +77,7 @@
                                        MachineBasicBlock::iterator I,
                                        unsigned DestReg, unsigned SrcReg,
                                        const TargetRegisterClass *RC) const {
-  if (RC == SparcV8::IntRegsRegisterClass) 
+  if (RC == SparcV8::IntRegsRegisterClass)
     BuildMI (MBB, I, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
   else if (RC == SparcV8::FPRegsRegisterClass)
     BuildMI (MBB, I, V8::FMOVS, 1, DestReg).addReg (SrcReg);


Index: llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h
diff -u llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.4 llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.5
--- llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h:1.4	Sun Aug 15 17:15:11 2004
+++ llvm/lib/Target/SparcV8/SparcV8RegisterInfo.h	Thu Apr 21 18:21:30 2005
@@ -1,10 +1,10 @@
 //===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
 // This file contains the SparcV8 implementation of the MRegisterInfo class.
@@ -33,7 +33,7 @@
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIndex) const;
-  
+
   void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
                     unsigned DestReg, unsigned SrcReg,
                     const TargetRegisterClass *RC) const;


Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.25 llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.26
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.25	Sun Dec 12 11:40:27 2004
+++ llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp	Thu Apr 21 18:21:30 2005
@@ -1,12 +1,12 @@
 //===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 //
 //===----------------------------------------------------------------------===//
 
@@ -87,7 +87,7 @@
   // Print LLVM code input to instruction selector:
   if (PrintMachineCode)
     PM.add(new PrintFunctionPass());
-  
+
   PM.add(createSparcV8SimpleInstructionSelector(*this));
 
   // Print machine instructions as they were initially generated.
@@ -126,7 +126,7 @@
 
   // Replace malloc and free instructions with library calls.
   PM.add(createLowerAllocationsPass());
-  
+
   // FIXME: implement the switch instruction in the instruction selector.
   PM.add(createLowerSwitchPass());
 
@@ -134,17 +134,17 @@
   PM.add(createLowerInvokePass());
 
   PM.add(createLowerConstantExpressionsPass());
-  
+
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
   // FIXME: implement the select instruction in the instruction selector.
   PM.add(createLowerSelectPass());
-  
+
   // Print LLVM code input to instruction selector:
   if (PrintMachineCode)
     PM.add(new PrintFunctionPass());
-  
+
   PM.add(createSparcV8SimpleInstructionSelector(TM));
 
   // Print machine instructions as they were initially generated.


Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.h
diff -u llvm/lib/Target/SparcV8/SparcV8TargetMachine.h:1.4 llvm/lib/Target/SparcV8/SparcV8TargetMachine.h:1.5
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.h:1.4	Sat Oct  9 00:57:01 2004
+++ llvm/lib/Target/SparcV8/SparcV8TargetMachine.h	Thu Apr 21 18:21:30 2005
@@ -1,12 +1,12 @@
 //===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file declares the SparcV8 specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
@@ -52,7 +52,7 @@
   ///
   virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
                                           MachineCodeEmitter &MCE);
-  
+
   virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
 };
 






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