[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
Chris Lattner
lattner at cs.uiuc.edu
Mon Apr 18 22:05:39 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PowerPCInstrFormats.td updated: 1.40 -> 1.41
---
Log message:
Now that the ppc64 and vmx operands of I are always 0, forward substitute
them away.
---
Diffs of the changes: (+30 -36)
PowerPCInstrFormats.td | 66 ++++++++++++++++++++++---------------------------
1 files changed, 30 insertions(+), 36 deletions(-)
Index: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.40 llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.41
--- llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.40 Tue Apr 19 00:00:59 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrFormats.td Tue Apr 19 00:05:22 2005
@@ -42,12 +42,11 @@
//
// PowerPC instruction formats
-class I<bits<6> opcode, bit ppc64, bit vmx, dag OL, string asmstr>
- : Instruction {
+class I<bits<6> opcode, dag OL, string asmstr> : Instruction {
field bits<32> Inst;
- bit PPC64 = ppc64;
- bit VMX = vmx;
+ bit PPC64 = 0; // Default value, override with isPPC64
+ bit VMX = 0; // Default value, override with isVMX
let Name = "";
let Namespace = "PPC";
@@ -58,7 +57,7 @@
// 1.7.1 I-Form
class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<24> LI;
let Inst{6-29} = LI;
@@ -67,8 +66,8 @@
}
// 1.7.2 B-Form
-class BForm<bits<6> opcode, bit aa, bit lk,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+class BForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr>
+ : I<opcode, OL, asmstr> {
bits<5> BO;
bits<3> CRNum;
bits<2> BICode;
@@ -90,8 +89,7 @@
}
// 1.7.4 D-Form
-class DForm_base<bits<6> opcode, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+class DForm_base<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr>{
bits<5> A;
bits<5> B;
bits<16> C;
@@ -101,8 +99,7 @@
let Inst{16-31} = C;
}
-class DForm_1<bits<6> opcode, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+class DForm_1<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<5> A;
bits<16> C;
bits<5> B;
@@ -116,7 +113,7 @@
: DForm_base<opcode, OL, asmstr>;
class DForm_2_r0<bits<6> opcode, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<5> A;
bits<16> B;
@@ -129,8 +126,7 @@
class DForm_3<bits<6> opcode, dag OL, string asmstr>
: DForm_1<opcode, OL, asmstr>;
-class DForm_4<bits<6> opcode, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+class DForm_4<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<5> B;
bits<5> A;
bits<16> C;
@@ -147,8 +143,7 @@
let C = 0;
}
-class DForm_5<bits<6> opcode, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+class DForm_5<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<3> BF;
bits<1> L;
bits<5> RA;
@@ -184,7 +179,7 @@
// 1.7.5 DS-Form
class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<5> RST;
bits<14> DS;
bits<5> RA;
@@ -200,8 +195,7 @@
// 1.7.6 X-Form
class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc,
- dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<5> RST;
bits<5> A;
bits<5> B;
@@ -217,7 +211,7 @@
// when code is emitted.
class XForm_base_r3xo_swapped
<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<5> A;
bits<5> RST;
bits<5> B;
@@ -249,7 +243,7 @@
}
class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<3> BF;
bits<1> L;
bits<5> RA;
@@ -270,7 +264,7 @@
}
class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<3> BF;
bits<5> FRA;
bits<5> FRB;
@@ -298,7 +292,7 @@
// 1.7.7 XL-Form
class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<3> CRD;
bits<2> CRDb;
bits<3> CRA;
@@ -317,7 +311,7 @@
}
class XLForm_2<bits<6> opcode, bits<10> xo, bit lk,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+ dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<5> BO;
bits<5> BI;
bits<2> BH;
@@ -339,7 +333,7 @@
}
class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<3> BF;
bits<3> BFA;
@@ -354,7 +348,7 @@
// 1.7.8 XFX-Form
class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<5> RT;
bits<10> SPR;
@@ -370,8 +364,8 @@
let SPR = spr;
}
-class XFXForm_3<bits<6> opcode, bits<10> xo,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : I<opcode, OL, asmstr> {
bits<5> RT;
let Inst{6-10} = RT;
@@ -381,7 +375,7 @@
}
class XFXForm_5<bits<6> opcode, bit mfcrf, bits<10> xo,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+ dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<8> FXM;
bits<5> ST;
@@ -403,8 +397,8 @@
}
// 1.7.10 XS-Form
-class XSForm_1<bits<6> opcode, bits<9> xo, bit rc,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+class XSForm_1<bits<6> opcode, bits<9> xo, bit rc, dag OL, string asmstr>
+ : I<opcode, OL, asmstr> {
bits<5> RS;
bits<5> A;
bits<6> SH;
@@ -419,7 +413,7 @@
// 1.7.11 XO-Form
class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, bit rc,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+ dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<5> RT;
bits<5> RA;
bits<5> RB;
@@ -447,7 +441,7 @@
// 1.7.12 A-Form
class AForm_1<bits<6> opcode, bits<5> xo, bit rc, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<5> FRT;
bits<5> FRA;
bits<5> FRC;
@@ -474,7 +468,7 @@
// 1.7.13 M-Form
class MForm_1<bits<6> opcode, bit rc, dag OL, string asmstr>
- : I<opcode, 0, 0, OL, asmstr> {
+ : I<opcode, OL, asmstr> {
bits<5> RA;
bits<5> RS;
bits<5> RB;
@@ -495,7 +489,7 @@
// 1.7.14 MD-Form
class MDForm_1<bits<6> opcode, bits<3> xo, bit rc,
- dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
+ dag OL, string asmstr> : I<opcode, OL, asmstr> {
bits<5> RS;
bits<5> RA;
bits<6> SH;
@@ -512,7 +506,7 @@
//===----------------------------------------------------------------------===//
-class Pseudo<dag OL, string asmstr> : I<0, 0, 0, OL, asmstr> {
+class Pseudo<dag OL, string asmstr> : I<0, OL, asmstr> {
let PPC64 = 0;
let VMX = 0;
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