[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC64ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.66 -> 1.67
PPC64ISelPattern.cpp updated: 1.7 -> 1.8
---
Log message:

Elimate handling of ZERO_EXTEND_INREG.  This causes the PPC backend to emit
andi instructions instead of rlwinm instructions for zero extend, but they
seem like they would take the same time.


---
Diffs of the changes:  (+0 -25)

 PPC32ISelPattern.cpp |   13 -------------
 PPC64ISelPattern.cpp |   12 ------------
 2 files changed, 25 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.66 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.67
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.66	Tue Apr 12 18:12:17 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Apr 12 21:40:26 2005
@@ -1636,19 +1636,6 @@
     }
     return Result;
     
-  case ISD::ZERO_EXTEND_INREG:
-    Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
-    default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break;
-    case MVT::i16:  Tmp2 = 16; break;
-    case MVT::i8:   Tmp2 = 24; break;
-    case MVT::i1:   Tmp2 = 31; break;
-    }
-    Opc = Recording ? PPC::RLWINMo : PPC::RLWINM;
-    RecordSuccess = true;
-    BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2).addImm(31);
-    return Result;
-    
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.7 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.8
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.7	Fri Apr  8 22:22:30 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Tue Apr 12 21:40:26 2005
@@ -1154,18 +1154,6 @@
     }
     return Result;
     
-  case ISD::ZERO_EXTEND_INREG:
-    Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
-    default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break;
-    case MVT::i16:  Tmp2 = 16; break;
-    case MVT::i8:   Tmp2 = 24; break;
-    case MVT::i1:   Tmp2 = 31; break;
-    }
-    BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2)
-      .addImm(31);
-    return Result;
-    
   case ISD::CopyFromReg:
     if (Result == 1)
       Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());