[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC64ISelPattern.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.52 -> 1.53
PPC64ISelPattern.cpp updated: 1.5 -> 1.6
---
Log message:

64b: Expand S/UREM
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
     Pattern match fsub a, mul(b, c) as fnmsub
     Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%


---
Diffs of the changes:  (+31 -7)

 PPC32ISelPattern.cpp |   34 +++++++++++++++++++++++++++-------
 PPC64ISelPattern.cpp |    4 ++++
 2 files changed, 31 insertions(+), 7 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.52 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.53
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.52	Thu Apr  7 15:30:01 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Fri Apr  8 22:05:51 2005
@@ -1117,15 +1117,15 @@
       Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
     } else if (!NoExcessFPPrecision && 
-        ISD::SUB == N.getOperand(0).getOpcode() &&
+        ISD::ADD == N.getOperand(0).getOpcode() &&
         N.getOperand(0).Val->hasOneUse() &&
-        ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
-        N.getOperand(0).getOperand(0).Val->hasOneUse()) {
+        ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
+        N.getOperand(0).getOperand(1).Val->hasOneUse()) {
       ++FusedFP; // Statistic
-      Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
-      Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
-      Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
-      Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
+      Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(1));
+      Tmp3 = SelectExpr(N.getOperand(0).getOperand(0));
+      Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
     } else if (ISD::FABS == N.getOperand(0).getOpcode()) {
       Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
@@ -1181,6 +1181,16 @@
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
       return Result;
     }
+    if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
+        N.getOperand(1).Val->hasOneUse()) {
+      ++FusedFP; // Statistic
+      Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
+      Tmp3 = SelectExpr(N.getOperand(0));
+      Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
+      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+      return Result;
+    }
     Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
@@ -1198,6 +1208,16 @@
       BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
       return Result;
     }
+    if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
+        N.getOperand(1).Val->hasOneUse()) {
+      ++FusedFP; // Statistic
+      Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
+      Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
+      Tmp3 = SelectExpr(N.getOperand(0));
+      Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
+      BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
+      return Result;
+    }
     Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.5 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.6
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.5	Fri Apr  8 18:45:01 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Fri Apr  8 22:05:51 2005
@@ -55,6 +55,10 @@
       setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
       setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
 
+      // PowerPC has no SREM/UREM instructions
+      setOperationAction(ISD::SREM, MVT::i64, Expand);
+      setOperationAction(ISD::UREM, MVT::i64, Expand);
+
       setShiftAmountFlavor(Extend);   // shl X, 32 == 0
       addLegalFPImmediate(+0.0); // Necessary for FSEL
       addLegalFPImmediate(-0.0); //