[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.36 -> 1.37
---
Log message:

Fold loads into sign/zero extends.  instead of:

  mov %AL, BYTE PTR [%EDX + l18_length_code]
  movzx %EAX, %AL

Emit:

  movzx %EAX, BYTE PTR [%EDX + l18_length_code]




---
Diffs of the changes:  (+25 -2)

Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.36 llvm/lib/Target/X86/X86ISelPattern.cpp:1.37
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.36	Tue Jan 11 17:21:30 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Tue Jan 11 17:33:00 2005
@@ -1011,18 +1011,31 @@
   case ISD::ZERO_EXTEND: {
     int DestIs16 = N.getValueType() == MVT::i16;
     int SrcIs16  = N.getOperand(0).getValueType() == MVT::i16;
-    Tmp1 = SelectExpr(N.getOperand(0));
 
     // FIXME: This hack is here for zero extension casts from bool to i8.  This
     // would not be needed if bools were promoted by Legalize.
     if (N.getValueType() == MVT::i8) {
+      Tmp1 = SelectExpr(N.getOperand(0));
       BuildMI(BB, X86::MOV8rr, 1, Result).addReg(Tmp1);
       return Result;
     }
 
+    if (isFoldableLoad(N.getOperand(0))) {
+      static const unsigned Opc[3] = {
+        X86::MOVZX32rm8, X86::MOVZX32rm16, X86::MOVZX16rm8
+      };
+
+      X86AddressMode AM;
+      EmitFoldedLoad(N.getOperand(0), AM);
+      addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
+                             
+      return Result;
+    }
+
     static const unsigned Opc[3] = {
       X86::MOVZX32rr8, X86::MOVZX32rr16, X86::MOVZX16rr8
     };
+    Tmp1 = SelectExpr(N.getOperand(0));
     BuildMI(BB, Opc[SrcIs16+DestIs16*2], 1, Result).addReg(Tmp1);
     return Result;
   }    
@@ -1034,6 +1047,17 @@
     assert(N.getOperand(0).getValueType() != MVT::i1 &&
            "Sign extend from bool not implemented!");
 
+   if (isFoldableLoad(N.getOperand(0))) {
+      static const unsigned Opc[3] = {
+        X86::MOVSX32rm8, X86::MOVSX32rm16, X86::MOVSX16rm8
+      };
+
+      X86AddressMode AM;
+      EmitFoldedLoad(N.getOperand(0), AM);
+      addFullAddress(BuildMI(BB, Opc[SrcIs16+DestIs16*2], 4, Result), AM);
+      return Result;
+    }
+
     static const unsigned Opc[3] = {
       X86::MOVSX32rr8, X86::MOVSX32rr16, X86::MOVSX16rr8
     };
@@ -2164,7 +2188,6 @@
                 return;
               }
             }
-            //Opc = TabPtr[Opc];
           }
         }
       }