[llvm-commits] CVS: llvm/lib/Target/Target.td

[Nate Begeman]

Changes in directory llvm/lib/Target:

Target.td updated: 1.39 -> 1.40
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Log message:

Add support for the isLoad and isStore flags, needed by the instruction scheduler

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Diffs of the changes:  (+2 -0)

Index: llvm/lib/Target/Target.td
diff -u llvm/lib/Target/Target.td:1.39 llvm/lib/Target/Target.td:1.40
--- llvm/lib/Target/Target.td:1.39	Tue Sep 28 13:34:14 2004
+++ llvm/lib/Target/Target.td	Tue Sep 28 16:29:00 2004
@@ -130,6 +130,8 @@
   bit isBranch     = 0;     // Is this instruction a branch instruction?
   bit isBarrier    = 0;     // Can control flow fall through this instruction?
   bit isCall       = 0;     // Is this instruction a call instruction?
+  bit isLoad       = 0;     // Is this instruction a load instruction?
+  bit isStore      = 0;     // Is this instruction a store instruction?
   bit isTwoAddress = 0;     // Is this a two address instruction?
   bit isTerminator = 0;     // Is this part of the terminator for a basic block?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?