[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.h

[Misha Brukman]

Changes in directory llvm/lib/Target/PowerPC:

PowerPCInstrInfo.h updated: 1.6 -> 1.7
---
Log message:

The PowerPCInstrInfo class has gone away.


---
Diffs of the changes:  (+0 -34)

Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.h
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.6 llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.7
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.h:1.6	Wed Aug 11 18:45:43 2004
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.h	Tue Aug 17 00:00:46 2004
@@ -15,7 +15,6 @@
 #define POWERPC_INSTRUCTIONINFO_H
 
 #include "PowerPC.h"
-#include "PowerPCRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
 namespace llvm {
@@ -62,39 +61,6 @@
 	};
 }
 
-class PowerPCInstrInfo : public TargetInstrInfo {
-  const PowerPCRegisterInfo RI;
-  bool is64bit;
-public:
-  PowerPCInstrInfo(bool is64b);
-
-  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
-  /// such, whenever a client has an instance of instruction info, it should
-  /// always be able to get register info as well (through this method).
-  ///
-  virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
-
-  //
-  // Return true if the instruction is a register to register move and
-  // leave the source and dest operands in the passed parameters.
-  //
-  virtual bool isMoveInstr(const MachineInstr& MI,
-                           unsigned& sourceReg,
-                           unsigned& destReg) const;
-
-  static unsigned invertPPCBranchOpcode(unsigned Opcode) {
-    switch (Opcode) {
-    default: assert(0 && "Unknown PPC branch opcode!");
-    case PPC::BEQ: return PPC::BNE;
-    case PPC::BNE: return PPC::BEQ;
-    case PPC::BLT: return PPC::BGE;
-    case PPC::BGE: return PPC::BLT;
-    case PPC::BGT: return PPC::BLE;
-    case PPC::BLE: return PPC::BGT;
-    } 
-  }
-};
-
 }
 
 #endif