[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h SparcV9InstrSelectionSupport.h
Brian Gaeke
gaeke at cs.uiuc.edu
Tue Jul 27 10:43:32 PDT 2004
Changes in directory llvm/lib/Target/SparcV9:
SparcV9InstrInfo.h updated: 1.7 -> 1.8
SparcV9InstrSelectionSupport.h updated: 1.18 -> 1.19
---
Log message:
As it happens, none of these TargetInstrInfo methods which are only
used in the SparcV9 backend really have anything to do with
TargetInstrInfo, so we're converting them into regular old global
functions and moving their declarations to SparcV9InstrSelectionSupport.h.
(They're mostly used as helper functions for SparcV9InstrSelection.)
---
Diffs of the changes: (+90 -104)
Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.7 llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.8
--- llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.7 Sun May 30 03:29:16 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.h Tue Jul 27 12:43:22 2004
@@ -68,110 +68,6 @@
// 2 other groups, including NOPs if necessary).
return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
}
-
- //-------------------------------------------------------------------------
- // Queries about representation of LLVM quantities (e.g., constants)
- //-------------------------------------------------------------------------
-
- virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
- const Instruction* I) const;
-
- //-------------------------------------------------------------------------
- // Code generation support for creating individual machine instructions
- //-------------------------------------------------------------------------
-
- // Get certain common op codes for the current target. This and all the
- // Create* methods below should be moved to a machine code generation class
- //
- virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
-
- // Get the value of an integral constant in the form that must
- // be put into the machine register. The specified constant is interpreted
- // as (i.e., converted if necessary to) the specified destination type. The
- // result is always returned as an uint64_t, since the representation of
- // int64_t and uint64_t are identical. The argument can be any known const.
- //
- // isValidConstant is set to true if a valid constant was found.
- //
- virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
- const Value *V,
- const Type *destType,
- bool &isValidConstant) const;
-
- // Create an instruction sequence to put the constant `val' into
- // the virtual register `dest'. `val' may be a Constant or a
- // GlobalValue, viz., the constant address of a global variable or function.
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- //
- virtual void CreateCodeToLoadConst(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const;
-
- // Create an instruction sequence to copy an integer value `val'
- // to a floating point value `dest' by copying to memory and back.
- // val must be an integral type. dest must be a Float or Double.
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- //
- virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const;
-
- // Similarly, create an instruction sequence to copy an FP value
- // `val' to an integer value `dest' by copying to memory and back.
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- //
- virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
- Function* F,
- Value* val,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const;
-
- // Create instruction(s) to copy src to dest, for arbitrary types
- // The generated instructions are returned in `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- //
- virtual void CreateCopyInstructionsByType(const TargetMachine& target,
- Function* F,
- Value* src,
- Instruction* dest,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const;
-
- // Create instruction sequence to produce a sign-extended register value
- // from an arbitrary sized value (sized in bits, not bytes).
- // The generated instructions are appended to `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- //
- virtual void CreateSignExtensionInstructions(const TargetMachine& target,
- Function* F,
- Value* srcVal,
- Value* destVal,
- unsigned int numLowBits,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const;
-
- // Create instruction sequence to produce a zero-extended register value
- // from an arbitrary sized value (sized in bits, not bytes).
- // The generated instructions are appended to `mvec'.
- // Any temp. registers (TmpInstruction) created are recorded in mcfi.
- //
- virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
- Function* F,
- Value* srcVal,
- Value* destVal,
- unsigned int numLowBits,
- std::vector<MachineInstr*>& mvec,
- MachineCodeForInstruction& mcfi) const;
};
} // End llvm namespace
Index: llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.18 llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.19
--- llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h:1.18 Thu Jul 1 23:57:35 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h Tue Jul 27 12:43:22 2004
@@ -226,6 +226,96 @@
const TargetMachine& targetMachine, bool canUseImmed,
unsigned& getMachineRegNum, int64_t& getImmedValue);
+/// ConvertConstantToIntType - Get the value of an integral constant in the
+/// form that must be put into the machine register. The specified constant is
+/// interpreted as (i.e., converted if necessary to) the specified destination
+/// type. The result is always returned as an uint64_t, since the
+/// representation of int64_t and uint64_t are identical. The argument can be
+/// any known const. isValidConstant is set to true if a valid constant was
+/// found.
+///
+uint64_t ConvertConstantToIntType (const TargetMachine &target,
+ const Value *V, const Type *destType, bool &isValidConstant);
+
+/// ConstantMayNotFitInImmedField - Test if this constant may not fit in the
+/// immediate field of the machine instructions (probably) generated for this
+/// instruction.
+///
+bool ConstantMayNotFitInImmedField (const Constant *CV, const Instruction *I);
+
+/// CreateCodeToLoadConst - Create an instruction sequence to put the
+/// constant `val' into the virtual register `dest'. `val' may be a Constant
+/// or a GlobalValue, viz., the constant address of a global variable or
+/// function. The generated instructions are returned in `mvec'. Any temp.
+/// registers (TmpInstruction) created are recorded in mcfi.
+///
+void CreateCodeToLoadConst (const TargetMachine &target, Function *F,
+ Value *val, Instruction *dest, std::vector<MachineInstr*> &mvec,
+ MachineCodeForInstruction &mcfi);
+
+/// CreateSignExtensionInstructions - Create instruction sequence to produce a
+/// sign-extended register value from an arbitrary sized value (sized in bits,
+/// not bytes). The generated instructions are appended to `mvec'. Any temp.
+/// registers (TmpInstruction) created are recorded in mcfi.
+///
+void CreateSignExtensionInstructions (const TargetMachine &target,
+ Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits,
+ std::vector<MachineInstr*> &mvec, MachineCodeForInstruction &mcfi);
+
+/// CreateZeroExtensionInstructions - Create instruction sequence to produce a
+/// zero-extended register value from an arbitrary sized value (sized in bits,
+/// not bytes). The generated instructions are appended to `mvec'. Any temp.
+/// registers (TmpInstruction) created are recorded in mcfi.
+///
+void CreateZeroExtensionInstructions (const TargetMachine &target,
+ Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits,
+ std::vector<MachineInstr*> &mvec, MachineCodeForInstruction &mcfi);
+
+/// CreateCodeToCopyIntToFloat - Create an instruction sequence to copy an
+/// integer value `val' to a floating point value `dest' by copying to memory
+/// and back. val must be an integral type. dest must be a Float or Double.
+/// The generated instructions are returned in `mvec'. Any temp. registers
+/// (TmpInstruction) created are recorded in mcfi.
+///
+void CreateCodeToCopyIntToFloat (const TargetMachine &target,
+ Function *F, Value *val, Instruction *dest, std::vector<MachineInstr*> &mvec,
+ MachineCodeForInstruction &mcfi);
+
+/// CreateCodeToCopyFloatToInt - Create an instruction sequence to copy an FP
+/// value `val' to an integer value `dest' by copying to memory and back. The
+/// generated instructions are returned in `mvec'. Any temp. registers
+/// (TmpInstruction) created are recorded in mcfi.
+///
+void CreateCodeToCopyFloatToInt (const TargetMachine &target, Function *F,
+ Value *val, Instruction *dest, std::vector<MachineInstr*> &mvec,
+ MachineCodeForInstruction &mcfi);
+
+/// CreateCopyInstructionsByType - Create instruction(s) to copy src to dest,
+/// for arbitrary types The generated instructions are returned in `mvec'. Any
+/// temp. registers (TmpInstruction) created are recorded in mcfi.
+///
+void CreateCopyInstructionsByType (const TargetMachine &target,
+ Function *F, Value *src, Instruction *dest, std::vector<MachineInstr*> &mvec,
+ MachineCodeForInstruction &mcfi);
+
+/// CreateSignExtensionInstructions - Create instruction sequence to produce a
+/// sign-extended register value from an arbitrary sized value (sized in bits,
+/// not bytes). The generated instructions are appended to `mvec'. Any temp.
+/// registers (TmpInstruction) created are recorded in mcfi.
+///
+void CreateSignExtensionInstructions (const TargetMachine &target,
+ Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits,
+ std::vector<MachineInstr*> &mvec, MachineCodeForInstruction &mcfi);
+
+/// CreateZeroExtensionInstructions - Create instruction sequence to produce a
+/// zero-extended register value from an arbitrary sized value (sized in bits,
+/// not bytes). The generated instructions are appended to `mvec'. Any temp.
+/// registers (TmpInstruction) created are recorded in mcfi.
+///
+void CreateZeroExtensionInstructions (const TargetMachine &target,
+ Function *F, Value *srcVal, Value *destVal, unsigned int numLowBits,
+ std::vector<MachineInstr*> &mvec, MachineCodeForInstruction &mcfi);
+
} // End llvm namespace
#endif
More information about the llvm-commits
mailing list