[llvm-commits] CVS: llvm/lib/CodeGen/MachineInstr.cpp MachineBasicBlock.cpp LiveIntervals.cpp VirtRegMap.cpp TwoAddressInstructionPass.cpp RegAllocSimple.cpp
Tanya Brethour
tbrethou at niobe.cs.uiuc.edu
Thu Jun 24 19:14:01 PDT 2004
Changes in directory llvm/lib/CodeGen:
MachineInstr.cpp updated: 1.101 -> 1.102
MachineBasicBlock.cpp updated: 1.15 -> 1.16
LiveIntervals.cpp updated: 1.78 -> 1.79
VirtRegMap.cpp updated: 1.13 -> 1.14
TwoAddressInstructionPass.cpp updated: 1.19 -> 1.20
RegAllocSimple.cpp updated: 1.56 -> 1.57
---
Log message:
Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.
---
Diffs of the changes: (+32 -19)
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.101 llvm/lib/CodeGen/MachineInstr.cpp:1.102
--- llvm/lib/CodeGen/MachineInstr.cpp:1.101 Thu Jun 17 17:26:53 2004
+++ llvm/lib/CodeGen/MachineInstr.cpp Thu Jun 24 19:13:11 2004
@@ -235,8 +235,14 @@
}
static void print(const MachineOperand &MO, std::ostream &OS,
- const TargetMachine &TM) {
- const MRegisterInfo *MRI = TM.getRegisterInfo();
+ const TargetMachine *TM) {
+
+ const MRegisterInfo *MRI = 0;
+
+ if(TM)
+ MRI = TM->getRegisterInfo();
+
+
bool CloseParen = true;
if (MO.isHiBits32())
OS << "%lm(";
@@ -313,7 +319,7 @@
OS << ")";
}
-void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
+void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
unsigned StartOp = 0;
// Specialize printing if op#0 is definition
@@ -322,7 +328,11 @@
OS << " = ";
++StartOp; // Don't print this operand again!
}
- OS << TM.getInstrInfo()->getName(getOpcode());
+
+ //Must check if Target machine is not null because machine BB could not
+ //be attached to a Machine function yet
+ if(TM)
+ OS << TM->getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
@@ -361,7 +371,10 @@
// info for the instruction.
if (const MachineBasicBlock *MBB = MI.getParent()) {
const MachineFunction *MF = MBB->getParent();
- MI.print(os, MF->getTarget());
+ if(MF)
+ MI.print(os, &MF->getTarget());
+ else
+ MI.print(os, 0);
return os;
}
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.15 llvm/lib/CodeGen/MachineBasicBlock.cpp:1.16
--- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.15 Thu Jun 17 17:26:53 2004
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp Thu Jun 24 19:13:11 2004
@@ -105,6 +105,6 @@
<< ", LLVM BB @" << (const void*) LBB << "):\n";
for (const_iterator I = begin(); I != end(); ++I) {
OS << "\t";
- I->print(OS, getParent()->getTarget());
+ I->print(OS, &getParent()->getTarget());
}
}
Index: llvm/lib/CodeGen/LiveIntervals.cpp
diff -u llvm/lib/CodeGen/LiveIntervals.cpp:1.78 llvm/lib/CodeGen/LiveIntervals.cpp:1.79
--- llvm/lib/CodeGen/LiveIntervals.cpp:1.78 Mon Jun 21 08:10:56 2004
+++ llvm/lib/CodeGen/LiveIntervals.cpp Thu Jun 24 19:13:11 2004
@@ -179,7 +179,7 @@
for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) {
std::cerr << getInstructionIndex(mii) << '\t';
- mii->print(std::cerr, *tm_);
+ mii->print(std::cerr, tm_);
}
});
@@ -427,7 +427,7 @@
const TargetInstrDescriptor& tid =
tm_->getInstrInfo()->get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
- mi->print(std::cerr, *tm_));
+ mi->print(std::cerr, tm_));
// handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
@@ -467,7 +467,7 @@
mi != mie; ++mi) {
const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
- mi->print(std::cerr, *tm_););
+ mi->print(std::cerr, tm_););
// we only join virtual registers with allocatable
// physical registers since we do not have liveness information
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.13 llvm/lib/CodeGen/VirtRegMap.cpp:1.14
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.13 Wed Jun 2 00:57:12 2004
+++ llvm/lib/CodeGen/VirtRegMap.cpp Thu Jun 24 19:13:11 2004
@@ -149,7 +149,7 @@
mf.getSSARegMap()->getRegClass(virtReg));
loaded[virtReg] = true;
DEBUG(std::cerr << '\t';
- prior(mii)->print(std::cerr, tm));
+ prior(mii)->print(std::cerr, &tm));
++numLoads;
}
if (mop.isDef() &&
@@ -165,7 +165,7 @@
mii->SetMachineOperandReg(i, physReg);
}
}
- DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm));
+ DEBUG(std::cerr << '\t'; mii->print(std::cerr, &tm));
loaded.clear();
}
}
@@ -231,9 +231,9 @@
mri_->getRegClass(physReg));
++numStores;
DEBUG(std::cerr << "added: ";
- prior(nextLastRef)->print(std::cerr, *tm_);
+ prior(nextLastRef)->print(std::cerr, tm_);
std::cerr << "after: ";
- lastDef->print(std::cerr, *tm_));
+ lastDef->print(std::cerr, tm_));
lastDef_[virtReg] = 0;
}
p2vMap_[physReg] = 0;
@@ -263,7 +263,7 @@
mri_->getRegClass(physReg));
++numLoads;
DEBUG(std::cerr << "added: ";
- prior(mii)->print(std::cerr, *tm_));
+ prior(mii)->print(std::cerr, tm_));
lastDef_[virtReg] = mii;
}
}
@@ -339,7 +339,7 @@
}
}
- DEBUG(std::cerr << '\t'; mii->print(std::cerr, *tm_));
+ DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm_));
}
for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.19 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.20
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.19 Wed Jun 2 00:57:12 2004
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Jun 24 19:13:11 2004
@@ -98,7 +98,7 @@
++numTwoAddressInstrs;
- DEBUG(std::cerr << '\t'; mi->print(std::cerr, TM));
+ DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
assert(mi->getOperand(1).isRegister() &&
mi->getOperand(1).getReg() &&
@@ -140,7 +140,7 @@
MachineBasicBlock::iterator prevMi = prior(mi);
DEBUG(std::cerr << "\t\tprepend:\t";
- prevMi->print(std::cerr, TM));
+ prevMi->print(std::cerr, &TM));
if (LV) {
// update live variables for regA
@@ -170,7 +170,7 @@
mi->RemoveOperand(1);
DEBUG(std::cerr << "\t\trewrite to:\t";
- mi->print(std::cerr, TM));
+ mi->print(std::cerr, &TM));
}
}
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.56 llvm/lib/CodeGen/RegAllocSimple.cpp:1.57
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.56 Wed Jun 2 00:57:12 2004
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Thu Jun 24 19:13:11 2004
@@ -177,7 +177,7 @@
unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, *TM));
+ MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
More information about the llvm-commits
mailing list