[llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp PhyRegAlloc.cpp PhyRegAlloc.h
Chris Lattner
lattner at cs.uiuc.edu
Wed Jun 2 01:03:08 PDT 2004
Changes in directory llvm/lib/Target/SparcV9/RegAlloc:
LiveRangeInfo.cpp updated: 1.52 -> 1.53
PhyRegAlloc.cpp updated: 1.149 -> 1.150
PhyRegAlloc.h updated: 1.66 -> 1.67
---
Log message:
Convert to the new TargetMachine interface.
---
Diffs of the changes: (+24 -24)
Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.52 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.53
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.52 Fri Apr 23 13:15:47 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp Wed Jun 2 00:55:00 2004
@@ -29,7 +29,7 @@
LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm,
std::vector<RegClass *> &RCL)
- : Meth(F), TM(tm), RegClassList(RCL), MRI(tm.getRegInfo()) { }
+ : Meth(F), TM(tm), RegClassList(RCL), MRI(*tm.getRegInfo()) { }
LiveRangeInfo::~LiveRangeInfo() {
@@ -176,8 +176,8 @@
// If the machine instruction is a call/return instruction, add it to
// CallRetInstrList for processing its args, ret value, and ret addr.
//
- if(TM.getInstrInfo().isReturn(MInst->getOpcode()) ||
- TM.getInstrInfo().isCall(MInst->getOpcode()))
+ if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) ||
+ TM.getInstrInfo()->isCall(MInst->getOpcode()))
CallRetInstrList.push_back(MInst);
// iterate over explicit MI operands and create a new LR
@@ -244,9 +244,9 @@
MachineInstr *MInst = *It;
MachineOpCode OpCode = MInst->getOpcode();
- if ((TM.getInstrInfo()).isReturn(OpCode))
+ if (TM.getInstrInfo()->isReturn(OpCode))
MRI.suggestReg4RetValue(MInst, *this);
- else if ((TM.getInstrInfo()).isCall(OpCode))
+ else if (TM.getInstrInfo()->isCall(OpCode))
MRI.suggestRegs4CallArgs(MInst, *this);
else
assert( 0 && "Non call/ret instr in CallRetInstrList" );
Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.149 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.150
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.149 Sun May 30 02:08:43 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Wed Jun 2 00:55:00 2004
@@ -240,7 +240,7 @@
// get the LV set after the instruction
const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
- bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpcode());
+ bool isCallInst = TM.getInstrInfo()->isCall(MInst->getOpcode());
if (isCallInst) {
// set the isCallInterference flag of each live range which extends
@@ -265,7 +265,7 @@
// another. This must be done because pseudo-instructions may be
// expanded to multiple instructions by the assembler, so all the
// operands must get distinct registers.
- if (TM.getInstrInfo().isPseudoInstr(MInst->getOpcode()))
+ if (TM.getInstrInfo()->isPseudoInstr(MInst->getOpcode()))
addInterf4PseudoInstr(MInst);
// Also add interference for any implicit definitions in a machine
@@ -453,7 +453,7 @@
// Now insert caller-saving code before/after the call.
// Do this before inserting spill code since some registers must be
// used by save/restore and spill code should not use those registers.
- if (TM.getInstrInfo().isCall(Opcode)) {
+ if (TM.getInstrInfo()->isCall(Opcode)) {
AddedInstrns &AI = AddedInstrMap[MInst];
insertCallerSavingCode(AI.InstrnsBefore, AI.InstrnsAfter, MInst,
MBB.getBasicBlock());
@@ -497,7 +497,7 @@
// their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
- if (! TM.getInstrInfo().isDummyPhiInstr(MII->getOpcode()))
+ if (! TM.getInstrInfo()->isDummyPhiInstr(MII->getOpcode()))
updateInstruction(MII, MBB);
// Now, move code out of delay slots of branches and returns if needed.
@@ -516,15 +516,15 @@
// If so, we need to handle spill differently but annulling is not yet used.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (unsigned delaySlots =
- TM.getInstrInfo().getNumDelaySlots(MII->getOpcode())) {
+ TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) {
MachineBasicBlock::iterator DelaySlotMI = next(MII);
assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
// Check the 2 conditions above:
// (1) Does a branch need instructions added after it?
// (2) O/w does delay slot instr. need instrns before or after?
- bool isBranch = (TM.getInstrInfo().isBranch(MII->getOpcode()) ||
- TM.getInstrInfo().isReturn(MII->getOpcode()));
+ bool isBranch = (TM.getInstrInfo()->isBranch(MII->getOpcode()) ||
+ TM.getInstrInfo()->isReturn(MII->getOpcode()));
bool cond1 = (isBranch &&
AddedInstrMap.count(MII) &&
AddedInstrMap[MII].InstrnsAfter.size() > 0);
@@ -549,7 +549,7 @@
// instruction out of the delay slot). On cond2 we need
// to insert a nop in place of the moved instruction
if (cond2) {
- MBB.insert(MII, BuildMI(TM.getInstrInfo().getNOPOpCode(),1));
+ MBB.insert(MII, BuildMI(TM.getInstrInfo()->getNOPOpCode(),1));
}
}
else {
@@ -565,7 +565,7 @@
MachineInstr *MInst = MII;
// do not process Phis
- if (TM.getInstrInfo().isDummyPhiInstr(MInst->getOpcode()))
+ if (TM.getInstrInfo()->isDummyPhiInstr(MInst->getOpcode()))
continue;
// if there are any added instructions...
@@ -573,11 +573,11 @@
AddedInstrns &CallAI = AddedInstrMap[MInst];
#ifndef NDEBUG
- bool isBranch = (TM.getInstrInfo().isBranch(MInst->getOpcode()) ||
- TM.getInstrInfo().isReturn(MInst->getOpcode()));
+ bool isBranch = (TM.getInstrInfo()->isBranch(MInst->getOpcode()) ||
+ TM.getInstrInfo()->isReturn(MInst->getOpcode()));
assert((!isBranch ||
AddedInstrMap[MInst].InstrnsAfter.size() <=
- TM.getInstrInfo().getNumDelaySlots(MInst->getOpcode())) &&
+ TM.getInstrInfo()->getNumDelaySlots(MInst->getOpcode())) &&
"Cannot put more than #delaySlots instrns after "
"branch or return! Need to handle temps differently.");
#endif
@@ -628,9 +628,9 @@
MachineInstr *MInst = MII;
const BasicBlock *BB = MBB.getBasicBlock();
- assert((! TM.getInstrInfo().isCall(MInst->getOpcode()) || OpNum == 0) &&
+ assert((! TM.getInstrInfo()->isCall(MInst->getOpcode()) || OpNum == 0) &&
"Outgoing arg of a call must be handled elsewhere (func arg ok)");
- assert(! TM.getInstrInfo().isReturn(MInst->getOpcode()) &&
+ assert(! TM.getInstrInfo()->isReturn(MInst->getOpcode()) &&
"Return value of a ret must be handled elsewhere");
MachineOperand& Op = MInst->getOperand(OpNum);
@@ -649,7 +649,7 @@
// trample those! Verify that the set is included in the LV set before MInst.
if (MII != MBB.begin()) {
MachineBasicBlock::iterator PredMI = prior(MII);
- if (unsigned DS = TM.getInstrInfo().getNumDelaySlots(PredMI->getOpcode()))
+ if (unsigned DS = TM.getInstrInfo()->getNumDelaySlots(PredMI->getOpcode()))
assert(set_difference(LVI->getLiveVarSetBeforeMInst(PredMI), LVSetBef)
.empty() && "Live-var set before branch should be included in "
"live-var set of each delay slot instruction!");
@@ -735,7 +735,7 @@
std::vector<MachineInstr*> &instrnsAfter,
MachineInstr *CallMI,
const BasicBlock *BB) {
- assert(TM.getInstrInfo().isCall(CallMI->getOpcode()));
+ assert(TM.getInstrInfo()->isCall(CallMI->getOpcode()));
// hash set to record which registers were saved/restored
hash_set<unsigned> PushedRegSet;
@@ -1326,8 +1326,8 @@
// Create each RegClass for the target machine and add it to the
// RegClassList. This must be done before calling constructLiveRanges().
for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
- RegClassList.push_back (new RegClass (Fn, &TM.getRegInfo (),
- MRI.getMachineRegClass (rc)));
+ RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
+ MRI.getMachineRegClass(rc)));
LRI->constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.66 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.67
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.66 Sat May 29 23:22:24 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h Wed Jun 2 00:55:00 2004
@@ -93,7 +93,7 @@
typedef std::map<const Function *, std::vector<AllocInfo> > SavedStateMapTy;
inline PhyRegAlloc (const TargetMachine &TM_) :
- TM (TM_), MRI (TM.getRegInfo ()),
+ TM (TM_), MRI (*TM.getRegInfo ()),
NumOfRegClasses (MRI.getNumOfRegClasses ()) { }
virtual ~PhyRegAlloc() { }
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