[llvm-commits] CVS: llvm/lib/Target/X86/InstSelectSimple.cpp

Chris Lattner lattner at cs.uiuc.edu
Sun Apr 11 20:44:02 PDT 2004


Changes in directory llvm/lib/Target/X86:

InstSelectSimple.cpp updated: 1.232 -> 1.233

---
Log message:

Use the fucomi[p] instructions to perform floating point comparisons instead
of the fucom[p][p] instructions.  This allows us to code generate this function

bool %test(double %X, double %Y) {
        %C = setlt double %Y, %X
        ret bool %C
}

... into:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucomip %ST(1)
        fstp %ST(0)
        setb %AL
        movsx %EAX, %AL
        ret 

where before we generated:

test:
        fld QWORD PTR [%ESP + 4]
        fld QWORD PTR [%ESP + 12]
        fucompp 
**      fnstsw 
**      sahf 
        setb %AL
        movsx %EAX, %AL
        ret 

The two marked instructions (which are the ones eliminated) are very bad, 
because they serialize execution of the processor.  These instructions are
available on the PPRO and later, but since we already use cmov's we aren't 
losing any portability.

I retained the old code for the day when we decide we want to support back
to the 386.



---
Diffs of the changes:  (+7 -3)

Index: llvm/lib/Target/X86/InstSelectSimple.cpp
diff -u llvm/lib/Target/X86/InstSelectSimple.cpp:1.232 llvm/lib/Target/X86/InstSelectSimple.cpp:1.233
--- llvm/lib/Target/X86/InstSelectSimple.cpp:1.232	Sun Apr 11 19:23:04 2004
+++ llvm/lib/Target/X86/InstSelectSimple.cpp	Sun Apr 11 20:43:36 2004
@@ -929,9 +929,13 @@
     BuildMI(*MBB, IP, X86::CMP32rr, 2).addReg(Op0r).addReg(Op1r);
     break;
   case cFP:
-    BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
-    BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
-    BuildMI(*MBB, IP, X86::SAHF, 1);
+    if (0) { // for processors prior to the P6
+      BuildMI(*MBB, IP, X86::FpUCOM, 2).addReg(Op0r).addReg(Op1r);
+      BuildMI(*MBB, IP, X86::FNSTSW8r, 0);
+      BuildMI(*MBB, IP, X86::SAHF, 1);
+    } else {
+      BuildMI(*MBB, IP, X86::FUCOMIr, 2).addReg(Op0r).addReg(Op1r);
+    }
     break;
 
   case cLong:





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