[llvm-commits] [parallel] CVS: llvm/include/llvm/Target/MRegisterInfo.h TargetData.h TargetFrameInfo.h TargetInstrInfo.h TargetMachine.h TargetMachineImpls.h TargetRegInfo.h TargetSchedInfo.h TargetCacheInfo.h
Misha Brukman
brukman at cs.uiuc.edu
Mon Mar 1 18:00:00 PST 2004
Changes in directory llvm/include/llvm/Target:
MRegisterInfo.h updated: 1.26 -> 1.26.4.1
TargetData.h updated: 1.22 -> 1.22.2.1
TargetFrameInfo.h updated: 1.9 -> 1.9.4.1
TargetInstrInfo.h updated: 1.53 -> 1.53.2.1
TargetMachine.h updated: 1.42 -> 1.42.2.1
TargetMachineImpls.h updated: 1.8 -> 1.8.2.1
TargetRegInfo.h updated: 1.47 -> 1.47.4.1
TargetSchedInfo.h updated: 1.21 -> 1.21.4.1
TargetCacheInfo.h (r1.12) removed
---
Log message:
Merge from trunk
---
Diffs of the changes: (+149 -147)
Index: llvm/include/llvm/Target/MRegisterInfo.h
diff -u llvm/include/llvm/Target/MRegisterInfo.h:1.26 llvm/include/llvm/Target/MRegisterInfo.h:1.26.4.1
--- llvm/include/llvm/Target/MRegisterInfo.h:1.26 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/Target/MRegisterInfo.h Mon Mar 1 17:57:19 2004
@@ -18,11 +18,13 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include <cassert>
+#include <functional>
namespace llvm {
class Type;
class MachineFunction;
+class MachineInstr;
/// MRegisterDesc - This record contains all of the information known about a
/// particular register. The AliasSet field (if not null) contains a pointer to
@@ -136,6 +138,20 @@
FirstVirtualRegister = 1024,
};
+ /// isPhysicalRegister - Return true if the specified register number is in
+ /// the physical register namespace.
+ static bool isPhysicalRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
+ return Reg < FirstVirtualRegister;
+ }
+
+ /// isVirtualRegister - Return true if the specified register number is in
+ /// the virtual register namespace.
+ static bool isVirtualRegister(unsigned Reg) {
+ assert(Reg && "this is not a register!");
+ return Reg >= FirstVirtualRegister;
+ }
+
const MRegisterDesc &operator[](unsigned RegNo) const {
assert(RegNo < NumRegs &&
"Attempting to access record for invalid register number!");
@@ -170,6 +186,20 @@
return get(RegNo).Name;
}
+ /// getNumRegs - Return the number of registers this target has
+ /// (useful for sizing arrays holding per register information)
+ unsigned getNumRegs() const {
+ return NumRegs;
+ }
+
+ /// areAliases - Returns true if the two registers alias each other,
+ /// false otherwise
+ bool areAliases(unsigned regA, unsigned regB) const {
+ for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
+ if (*Alias == regA) return true;
+ return false;
+ }
+
virtual const unsigned* getCalleeSaveRegs() const = 0;
@@ -208,21 +238,32 @@
//
virtual int storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineBasicBlock::iterator MI,
unsigned SrcReg, int FrameIndex,
const TargetRegisterClass *RC) const = 0;
virtual int loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC) const = 0;
virtual int copyRegToReg(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &MBBI,
+ MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *RC) const = 0;
+ /// foldMemoryOperand - If this target supports it, fold a load or store of
+ /// the specified stack slot into the specified machine instruction for the
+ /// specified operand. If this is possible, the target should perform the
+ /// folding and return true, otherwise it should return false. If it folds
+ /// the instruction, it is likely that the MachineInstruction the iterator
+ /// references has been changed.
+ virtual bool foldMemoryOperand(MachineBasicBlock::iterator &MI,
+ unsigned OpNum, int FrameIndex) const {
+ return false;
+ }
+
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
/// targets use pseudo instructions in order to abstract away the difference
@@ -241,14 +282,14 @@
/// setup/destroy pseudo instructions. The return value is the number of
/// instructions added to (negative if removed from) the basic block.
///
- virtual int eliminateCallFramePseudoInstr(MachineFunction &MF,
- MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) const {
+ virtual void
+ eliminateCallFramePseudoInstr(MachineFunction &MF,
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator MI) const {
assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
"eliminateCallFramePseudoInstr must be implemented if using"
" call frame setup/destroy pseudo instructions!");
assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
- return -1;
}
/// processFunctionBeforeFrameFinalized - This method is called immediately
@@ -258,8 +299,7 @@
/// is the number of instructions added to (negative if removed from) the
/// basic block
///
- virtual int processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
- return 0;
+ virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
}
/// eliminateFrameIndex - This method must be overriden to eliminate abstract
@@ -270,16 +310,23 @@
/// finished product. The return value is the number of instructions
/// added to (negative if removed from) the basic block.
///
- virtual int eliminateFrameIndex(MachineFunction &MF,
- MachineBasicBlock::iterator &II) const = 0;
+ virtual void eliminateFrameIndex(MachineFunction &MF,
+ MachineBasicBlock::iterator MI) const = 0;
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. The return value is the number of instructions
/// added to (negative if removed from) the basic block (entry for prologue).
///
- virtual int emitPrologue(MachineFunction &MF) const = 0;
- virtual int emitEpilogue(MachineFunction &MF,
- MachineBasicBlock &MBB) const = 0;
+ virtual void emitPrologue(MachineFunction &MF) const = 0;
+ virtual void emitEpilogue(MachineFunction &MF,
+ MachineBasicBlock &MBB) const = 0;
+};
+
+// This is useful when building DenseMap's keyed on virtual registers
+struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
+ unsigned operator()(unsigned Reg) const {
+ return Reg - MRegisterInfo::FirstVirtualRegister;
+ }
};
} // End llvm namespace
Index: llvm/include/llvm/Target/TargetData.h
diff -u llvm/include/llvm/Target/TargetData.h:1.22 llvm/include/llvm/Target/TargetData.h:1.22.2.1
--- llvm/include/llvm/Target/TargetData.h:1.22 Sun Dec 21 23:00:45 2003
+++ llvm/include/llvm/Target/TargetData.h Mon Mar 1 17:57:19 2004
@@ -21,9 +21,9 @@
#define LLVM_TARGET_TARGETDATA_H
#include "llvm/Pass.h"
-#include "Support/Annotation.h"
#include "Support/DataTypes.h"
#include <vector>
+#include <string>
namespace llvm {
@@ -42,9 +42,6 @@
unsigned char DoubleAlignment; // Defaults to 8 bytes
unsigned char PointerSize; // Defaults to 8 bytes
unsigned char PointerAlignment; // Defaults to 8 bytes
- AnnotationID AID; // AID for structure layout annotation
-
- static Annotation *TypeAnFactory(AnnotationID, const Annotable *, void *);
public:
TargetData(const std::string &TargetName = "",
bool LittleEndian = false,
@@ -69,7 +66,6 @@
unsigned char getDoubleAlignment() const { return DoubleAlignment; }
unsigned char getPointerAlignment() const { return PointerAlignment; }
unsigned char getPointerSize() const { return PointerSize; }
- AnnotationID getStructLayoutAID() const { return AID; }
/// getTypeSize - Return the number of bytes necessary to hold the specified
/// type
@@ -89,23 +85,19 @@
uint64_t getIndexedOffset(const Type *Ty,
const std::vector<Value*> &Indices) const;
- inline const StructLayout *getStructLayout(const StructType *Ty) const {
- return (const StructLayout*)
- ((const Annotable*)Ty)->getOrCreateAnnotation(AID);
- }
+ const StructLayout *getStructLayout(const StructType *Ty) const;
};
-// This annotation (attached ONLY to StructType classes) is used to lazily
-// calculate structure layout information for a target machine, based on the
-// TargetData structure.
+// This object is used to lazily calculate structure layout information for a
+// target machine, based on the TargetData structure.
//
-struct StructLayout : public Annotation {
+struct StructLayout {
std::vector<uint64_t> MemberOffsets;
uint64_t StructSize;
unsigned StructAlignment;
private:
friend class TargetData; // Only TargetData can create this class
- inline StructLayout(const StructType *ST, const TargetData &TD);
+ StructLayout(const StructType *ST, const TargetData &TD);
};
} // End llvm namespace
Index: llvm/include/llvm/Target/TargetFrameInfo.h
diff -u llvm/include/llvm/Target/TargetFrameInfo.h:1.9 llvm/include/llvm/Target/TargetFrameInfo.h:1.9.4.1
--- llvm/include/llvm/Target/TargetFrameInfo.h:1.9 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/Target/TargetFrameInfo.h Mon Mar 1 17:57:19 2004
@@ -14,6 +14,8 @@
#ifndef LLVM_TARGET_TARGETFRAMEINFO_H
#define LLVM_TARGET_TARGETFRAMEINFO_H
+#include <cstdlib>
+
namespace llvm {
class MachineFunction;
Index: llvm/include/llvm/Target/TargetInstrInfo.h
diff -u llvm/include/llvm/Target/TargetInstrInfo.h:1.53 llvm/include/llvm/Target/TargetInstrInfo.h:1.53.2.1
--- llvm/include/llvm/Target/TargetInstrInfo.h:1.53 Sun Dec 28 11:35:08 2003
+++ llvm/include/llvm/Target/TargetInstrInfo.h Mon Mar 1 17:57:19 2004
@@ -33,12 +33,9 @@
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------
-typedef int MachineOpCode;
+typedef short MachineOpCode;
typedef unsigned InstrSchedClass;
-const MachineOpCode INVALID_MACHINE_OPCODE = -1;
-
-
//---------------------------------------------------------------------------
// struct TargetInstrDescriptor:
// Predefined information about each machine instruction.
@@ -49,14 +46,8 @@
const unsigned M_BRANCH_FLAG = 1 << 1;
const unsigned M_CALL_FLAG = 1 << 2;
const unsigned M_RET_FLAG = 1 << 3;
-const unsigned M_ARITH_FLAG = 1 << 4;
const unsigned M_CC_FLAG = 1 << 6;
-const unsigned M_LOGICAL_FLAG = 1 << 6;
-const unsigned M_INT_FLAG = 1 << 7;
-const unsigned M_FLOAT_FLAG = 1 << 8;
-const unsigned M_CONDL_FLAG = 1 << 9;
const unsigned M_LOAD_FLAG = 1 << 10;
-const unsigned M_PREFETCH_FLAG = 1 << 11;
const unsigned M_STORE_FLAG = 1 << 12;
const unsigned M_DUMMY_PHI_FLAG = 1 << 13;
const unsigned M_PSEUDO_FLAG = 1 << 14; // Pseudo instruction
@@ -73,7 +64,7 @@
const char * Name; // Assembly language mnemonic for the opcode.
int numOperands; // Number of args; -1 if variable #args
int resultPos; // Position of the result; -1 if no result
- unsigned maxImmedConst; // Largest +ve constant in IMMMED field or 0.
+ unsigned maxImmedConst; // Largest +ve constant in IMMED field or 0.
bool immedIsSignExtended; // Is IMMED field sign-extended? If so,
// smallest -ve value is -(maxImmedConst+1).
unsigned numDelaySlots; // Number of delay slots after instruction
@@ -92,27 +83,25 @@
///
class TargetInstrInfo {
const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned descSize; // number of entries in the desc array
+ unsigned NumOpcodes; // number of entries in the desc array
unsigned numRealOpCodes; // number of non-dummy op codes
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
- unsigned numRealOpCodes);
+ TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
// Invariant: All instruction sets use opcode #0 as the PHI instruction
enum { PHI = 0 };
- unsigned getNumRealOpCodes() const { return numRealOpCodes; }
- unsigned getNumTotalOpCodes() const { return descSize; }
+ unsigned getNumOpcodes() const { return NumOpcodes; }
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
const TargetInstrDescriptor& get(MachineOpCode opCode) const {
- assert(opCode >= 0 && opCode < (int)descSize);
+ assert((unsigned)opCode < NumOpcodes);
return desc[opCode];
}
@@ -123,15 +112,8 @@
int getNumOperands(MachineOpCode opCode) const {
return get(opCode).numOperands;
}
-
- int getResultPos(MachineOpCode opCode) const {
- return get(opCode).resultPos;
- }
-
- unsigned getNumDelaySlots(MachineOpCode opCode) const {
- return get(opCode).numDelaySlots;
- }
-
+
+
InstrSchedClass getSchedClass(MachineOpCode opCode) const {
return get(opCode).schedClass;
}
@@ -144,66 +126,15 @@
return get(opCode).ImplicitDefs;
}
+
//
// Query instruction class flags according to the machine-independent
// flags listed above.
//
- bool isNop(MachineOpCode opCode) const {
- return get(opCode).Flags & M_NOP_FLAG;
- }
- bool isBranch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_BRANCH_FLAG;
- }
- bool isCall(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CALL_FLAG;
- }
bool isReturn(MachineOpCode opCode) const {
return get(opCode).Flags & M_RET_FLAG;
}
- bool isControlFlow(MachineOpCode opCode) const {
- return get(opCode).Flags & M_BRANCH_FLAG
- || get(opCode).Flags & M_CALL_FLAG
- || get(opCode).Flags & M_RET_FLAG;
- }
- bool isArith(MachineOpCode opCode) const {
- return get(opCode).Flags & M_ARITH_FLAG;
- }
- bool isCCInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CC_FLAG;
- }
- bool isLogical(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOGICAL_FLAG;
- }
- bool isIntInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_INT_FLAG;
- }
- bool isFloatInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_FLOAT_FLAG;
- }
- bool isConditional(MachineOpCode opCode) const {
- return get(opCode).Flags & M_CONDL_FLAG;
- }
- bool isLoad(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG;
- }
- bool isPrefetch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_PREFETCH_FLAG;
- }
- bool isLoadOrPrefetch(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG
- || get(opCode).Flags & M_PREFETCH_FLAG;
- }
- bool isStore(MachineOpCode opCode) const {
- return get(opCode).Flags & M_STORE_FLAG;
- }
- bool isMemoryAccess(MachineOpCode opCode) const {
- return get(opCode).Flags & M_LOAD_FLAG
- || get(opCode).Flags & M_PREFETCH_FLAG
- || get(opCode).Flags & M_STORE_FLAG;
- }
- bool isDummyPhiInstr(MachineOpCode opCode) const {
- return get(opCode).Flags & M_DUMMY_PHI_FLAG;
- }
+
bool isPseudoInstr(MachineOpCode opCode) const {
return get(opCode).Flags & M_PSEUDO_FLAG;
}
@@ -224,6 +155,45 @@
return false;
}
+
+
+
+ //-------------------------------------------------------------------------
+ // Code generation support for creating individual machine instructions
+ //
+ // WARNING: These methods are Sparc specific
+ //
+ // DO NOT USE ANY OF THESE METHODS THEY ARE DEPRECATED!
+ //
+ //-------------------------------------------------------------------------
+
+ int getResultPos(MachineOpCode opCode) const {
+ return get(opCode).resultPos;
+ }
+ unsigned getNumDelaySlots(MachineOpCode opCode) const {
+ return get(opCode).numDelaySlots;
+ }
+ bool isCCInstr(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_CC_FLAG;
+ }
+ bool isNop(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_NOP_FLAG;
+ }
+ bool isBranch(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_BRANCH_FLAG;
+ }
+ bool isCall(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_CALL_FLAG;
+ }
+ bool isLoad(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_LOAD_FLAG;
+ }
+ bool isStore(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_STORE_FLAG;
+ }
+ bool isDummyPhiInstr(MachineOpCode opCode) const {
+ return get(opCode).Flags & M_DUMMY_PHI_FLAG;
+ }
// Check if an instruction can be issued before its operands are ready,
// or if a subsequent instruction that uses its result can be issued
// before the results are ready.
@@ -231,8 +201,7 @@
//
virtual bool hasOperandInterlock(MachineOpCode opCode) const {
return true;
- }
-
+ }
virtual bool hasResultInterlock(MachineOpCode opCode) const {
return true;
}
@@ -261,7 +230,7 @@
virtual bool constantFitsInImmedField(MachineOpCode opCode,
int64_t intValue) const;
- // Return the largest +ve constant that can be held in the IMMMED field
+ // Return the largest positive constant that can be held in the IMMED field
// of this machine instruction.
// isSignExtended is set to true if the value is sign-extended before use
// (this is true for all immediate fields in SPARC instructions).
@@ -291,26 +260,6 @@
const Instruction* I) const {
return true; // safe but very conservative
}
-
-
- /// createNOPinstr - returns the target's implementation of NOP, which is
- /// usually a pseudo-instruction, implemented by a degenerate version of
- /// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi g0, 0
- ///
- virtual MachineInstr* createNOPinstr() const = 0;
-
- /// isNOPinstr - not having a special NOP opcode, we need to know if a given
- /// instruction is interpreted as an `official' NOP instr, i.e., there may be
- /// more than one way to `do nothing' but only one canonical way to slack off.
- ///
- virtual bool isNOPinstr(const MachineInstr &MI) const = 0;
-
- //-------------------------------------------------------------------------
- // Code generation support for creating individual machine instructions
- //
- // WARNING: These methods are Sparc specific
- //
- //-------------------------------------------------------------------------
// Get certain common op codes for the current target. this and all the
// Create* methods below should be moved to a machine code generation class
Index: llvm/include/llvm/Target/TargetMachine.h
diff -u llvm/include/llvm/Target/TargetMachine.h:1.42 llvm/include/llvm/Target/TargetMachine.h:1.42.2.1
--- llvm/include/llvm/Target/TargetMachine.h:1.42 Sun Dec 28 15:22:35 2003
+++ llvm/include/llvm/Target/TargetMachine.h Mon Mar 1 17:57:19 2004
@@ -25,7 +25,6 @@
class TargetSchedInfo;
class TargetRegInfo;
class TargetFrameInfo;
-class TargetCacheInfo;
class MachineCodeEmitter;
class MRegisterInfo;
class FunctionPassManager;
@@ -75,7 +74,6 @@
virtual const TargetSchedInfo& getSchedInfo() const = 0;
virtual const TargetRegInfo& getRegInfo() const = 0;
virtual const TargetFrameInfo& getFrameInfo() const = 0;
- virtual const TargetCacheInfo& getCacheInfo() const = 0;
const TargetData &getTargetData() const { return DataLayout; }
/// getRegisterInfo - If register information is available, return it. If
Index: llvm/include/llvm/Target/TargetMachineImpls.h
diff -u llvm/include/llvm/Target/TargetMachineImpls.h:1.8 llvm/include/llvm/Target/TargetMachineImpls.h:1.8.2.1
--- llvm/include/llvm/Target/TargetMachineImpls.h:1.8 Sun Dec 28 03:48:17 2003
+++ llvm/include/llvm/Target/TargetMachineImpls.h Mon Mar 1 17:57:19 2004
@@ -21,14 +21,30 @@
class Module;
class IntrinsicLowering;
- // allocateSparcTargetMachine - Allocate and return a subclass of
- // TargetMachine that implements the Sparc backend. This takes ownership of
- // the IntrinsicLowering pointer, deleting it when the target machine is
+ // allocateCTargetMachine - Allocate and return a subclass of TargetMachine
+ // that implements emits C code. This takes ownership of the
+ // IntrinsicLowering pointer, deleting it when the target machine is
// destroyed.
//
- TargetMachine *allocateSparcTargetMachine(const Module &M,
+ TargetMachine *allocateCTargetMachine(const Module &M,
+ IntrinsicLowering *IL = 0);
+
+ // allocateSparcV9TargetMachine - Allocate and return a subclass of
+ // TargetMachine that implements the 64-bit Sparc backend. This takes
+ // ownership of the IntrinsicLowering pointer, deleting it when the target
+ // machine is destroyed.
+ //
+ TargetMachine *allocateSparcV9TargetMachine(const Module &M,
IntrinsicLowering *IL = 0);
+ // allocateSparcV8TargetMachine - Allocate and return a subclass of
+ // TargetMachine that implements the 32-bit Sparc backend. This takes
+ // ownership of the IntrinsicLowering pointer, deleting it when the target
+ // machine is destroyed.
+ //
+ TargetMachine *allocateSparcV8TargetMachine(const Module &M,
+ IntrinsicLowering *IL = 0);
+
// allocateX86TargetMachine - Allocate and return a subclass of TargetMachine
// that implements the X86 backend. This takes ownership of the
// IntrinsicLowering pointer, deleting it when the target machine is
@@ -36,6 +52,14 @@
//
TargetMachine *allocateX86TargetMachine(const Module &M,
IntrinsicLowering *IL = 0);
+
+ // allocatePowerPCTargetMachine - Allocate and return a subclass
+ // of TargetMachine that implements the PowerPC backend. This takes
+ // ownership of the IntrinsicLowering pointer, deleting it when
+ // the target machine is destroyed.
+ //
+ TargetMachine *allocatePowerPCTargetMachine(const Module &M,
+ IntrinsicLowering *IL = 0);
} // End llvm namespace
#endif
Index: llvm/include/llvm/Target/TargetRegInfo.h
diff -u llvm/include/llvm/Target/TargetRegInfo.h:1.47 llvm/include/llvm/Target/TargetRegInfo.h:1.47.4.1
--- llvm/include/llvm/Target/TargetRegInfo.h:1.47 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/Target/TargetRegInfo.h Mon Mar 1 17:57:19 2004
@@ -149,7 +149,7 @@
// returns the register that is hardwired to zero if any (-1 if none)
//
- virtual int getZeroRegNum() const = 0;
+ virtual unsigned getZeroRegNum() const = 0;
// Number of registers used for passing int args (usually 6: %o0 - %o5)
// and float args (usually 32: %f0 - %f31)
Index: llvm/include/llvm/Target/TargetSchedInfo.h
diff -u llvm/include/llvm/Target/TargetSchedInfo.h:1.21 llvm/include/llvm/Target/TargetSchedInfo.h:1.21.4.1
--- llvm/include/llvm/Target/TargetSchedInfo.h:1.21 Tue Nov 11 16:41:31 2003
+++ llvm/include/llvm/Target/TargetSchedInfo.h Mon Mar 1 17:57:19 2004
@@ -191,16 +191,6 @@
unsigned maxNumIssueTotal;
int longestIssueConflict;
- int branchMispredictPenalty; // 4 for SPARC IIi
- int branchTargetUnknownPenalty; // 2 for SPARC IIi
- int l1DCacheMissPenalty; // 7 or 9 for SPARC IIi
- int l1ICacheMissPenalty; // ? for SPARC IIi
-
- bool inOrderLoads; // true for SPARC IIi
- bool inOrderIssue; // true for SPARC IIi
- bool inOrderExec; // false for most architectures
- bool inOrderRetire; // true for most architectures
-
protected:
inline const InstrRUsage& getInstrRUsage(MachineOpCode opCode) const {
assert(opCode >= 0 && opCode < (int) instrRUsages.size());
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