[llvm-commits] CVS: llvm/include/llvm/CodeGen/LiveIntervals.h

[Alkis Evlogimenos]

Changes in directory llvm/include/llvm/CodeGen:

LiveIntervals.h updated: 1.19 -> 1.20

---
Log message:

Too many changes in one commit:

1. LiveIntervals now implement a 4 slot per instruction model. Load,
   Use, Def and a Store slot. This is required in order to correctly
   represent caller saved register clobbering on function calls,
   register reuse in the same instruction (def resues last use) and
   also spill code added later by the allocator. The previous
   representation (2 slots per instruction) was insufficient and as a
   result was causing subtle bugs.

2. Fixes in spill code generation. This was the major cause of
   failures in the test suite.

3. Linear scan now has core support for folding memory operands. This
   is untested and not enabled (the live interval update function does
   not attempt to fold loads/stores in instructions).

4. Lots of improvements in the debugging output of both live intervals
   and linear scan. Give it a try... it is beautiful :-)

In summary the above fixes all the issues with the recent reserved
register elimination changes and get the allocator very close to the
next big step: folding memory operands.


---
Diffs of the changes:  (+33 -1)

Index: llvm/include/llvm/CodeGen/LiveIntervals.h
diff -u llvm/include/llvm/CodeGen/LiveIntervals.h:1.19 llvm/include/llvm/CodeGen/LiveIntervals.h:1.20
--- llvm/include/llvm/CodeGen/LiveIntervals.h:1.19	Wed Feb 18 17:14:52 2004
+++ llvm/include/llvm/CodeGen/LiveIntervals.h	Fri Feb 20 00:15:40 2004
@@ -44,6 +44,8 @@
 
             bool empty() const { return ranges.empty(); }
 
+            bool spilled() const;
+
             unsigned start() const {
                 assert(!empty() && "empty interval for register");
                 return ranges.front().first;
@@ -112,6 +114,33 @@
         Intervals intervals_;
 
     public:
+        struct InstrSlots
+        {
+            enum {
+                LOAD  = 0,
+                USE   = 1,
+                DEF   = 2,
+                STORE = 3,
+                NUM   = 4,
+            };
+        };
+
+        static unsigned getBaseIndex(unsigned index) {
+            return index - (index % 4);
+        }
+        static unsigned getLoadIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::LOAD;
+        }
+        static unsigned getUseIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::USE;
+        }
+        static unsigned getDefIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::DEF;
+        }
+        static unsigned getStoreIndex(unsigned index) {
+            return getBaseIndex(index) + InstrSlots::STORE;
+        }
+
         virtual void getAnalysisUsage(AnalysisUsage &AU) const;
         virtual void releaseMemory();
 
@@ -123,13 +152,16 @@
             return *r2iMap_.find(reg)->second;
         }
 
+        /// getInstructionIndex - returns the base index of instr
         unsigned getInstructionIndex(MachineInstr* instr) const;
 
+        /// getInstructionFromIndex - given an index in any slot of an
+        /// instruction return a pointer the instruction
         MachineInstr* getInstructionFromIndex(unsigned index) const;
 
         Intervals& getIntervals() { return intervals_; }
 
-        void updateSpilledInterval(Interval& i);
+        void updateSpilledInterval(Interval& i, int slot);
 
     private:
         /// computeIntervals - compute live intervals