[llvm-commits] CVS: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp InstrScheduling.cpp
Alkis Evlogimenos
alkis at cs.uiuc.edu
Wed Feb 11 20:28:32 PST 2004
Changes in directory llvm/lib/CodeGen/InstrSched:
SchedGraph.cpp updated: 1.56 -> 1.57
InstrScheduling.cpp updated: 1.64 -> 1.65
---
Log message:
Change MachineBasicBlock's vector of MachineInstr pointers into an
ilist of MachineInstr objects. This allows constant time removal and
insertion of MachineInstr instances from anywhere in each
MachineBasicBlock. It also allows for constant time splicing of
MachineInstrs into or out of MachineBasicBlocks.
---
Diffs of the changes: (+24 -23)
Index: llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
diff -u llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.56 llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.57
--- llvm/lib/CodeGen/InstrSched/SchedGraph.cpp:1.56 Wed Feb 11 19:34:05 2004
+++ llvm/lib/CodeGen/InstrSched/SchedGraph.cpp Wed Feb 11 20:27:10 2004
@@ -53,7 +53,8 @@
SchedGraphNode::SchedGraphNode(unsigned NID, MachineBasicBlock *mbb,
int indexInBB, const TargetMachine& Target)
- : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb), MI(mbb ? (*mbb)[indexInBB] : 0) {
+ : SchedGraphNodeCommon(NID,indexInBB), MBB(mbb),
+ MI(mbb ? &(*mbb)[indexInBB] : (MachineInstr*)0) {
if (MI) {
MachineOpCode mopCode = MI->getOpcode();
latency = Target.getInstrInfo().hasResultInterlock(mopCode)
@@ -183,10 +184,10 @@
// all preceding instructions in the basic block. Use 0 latency again.
//
for (unsigned i=0, N=MBB.size(); i < N; i++) {
- if (MBB[i] == termMvec[first]) // reached the first branch
+ if (&MBB[i] == termMvec[first]) // reached the first branch
break;
- SchedGraphNode* fromNode = this->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* fromNode = this->getGraphNodeForInstr(&MBB[i]);
if (fromNode == NULL)
continue; // dummy instruction, e.g., PHI
@@ -198,11 +199,11 @@
// the terminator) that also have delay slots, add an outgoing edge
// from the instruction to the instructions in the delay slots.
//
- unsigned d = mii.getNumDelaySlots(MBB[i]->getOpcode());
+ unsigned d = mii.getNumDelaySlots(MBB[i].getOpcode());
assert(i+d < N && "Insufficient delay slots for instruction?");
for (unsigned j=1; j <= d; j++) {
- SchedGraphNode* toNode = this->getGraphNodeForInstr(MBB[i+j]);
+ SchedGraphNode* toNode = this->getGraphNodeForInstr(&MBB[i+j]);
assert(toNode && "No node for machine instr in delay slot?");
(void) new SchedGraphEdge(fromNode, toNode,
SchedGraphEdge::CtrlDep,
@@ -554,9 +555,9 @@
// Build graph nodes for each VM instruction and gather def/use info.
// Do both those together in a single pass over all machine instructions.
for (unsigned i=0; i < MBB.size(); i++)
- if (!mii.isDummyPhiInstr(MBB[i]->getOpcode())) {
+ if (!mii.isDummyPhiInstr(MBB[i].getOpcode())) {
SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
- noteGraphNodeForInstr(MBB[i], node);
+ noteGraphNodeForInstr(&MBB[i], node);
// Remember all register references and value defs
findDefUseInfoAtInstr(target, node, memNodeVec, callDepNodeVec,
@@ -632,7 +633,7 @@
// Then add incoming def-use (SSA) edges for each machine instruction.
for (unsigned i=0, N=MBB.size(); i < N; i++)
- addEdgesForInstruction(*MBB[i], valueToDefVecMap, target);
+ addEdgesForInstruction(MBB[i], valueToDefVecMap, target);
// Then add edges for dependences on machine registers
this->addMachineRegEdges(regToRefVecMap, target);
Index: llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp
diff -u llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.64 llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.65
--- llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp:1.64 Wed Feb 11 19:34:05 2004
+++ llvm/lib/CodeGen/InstrSched/InstrScheduling.cpp Wed Feb 11 20:27:10 2004
@@ -630,8 +630,8 @@
// some NOPs from delay slots. Also, PHIs are not included in the schedule.
unsigned numInstr = 0;
for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
- if (! mii.isNop((*I)->getOpcode()) &&
- ! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isNop(I->getOpcode()) &&
+ ! mii.isDummyPhiInstr(I->getOpcode()))
++numInstr;
assert(S.isched.getNumInstructions() >= numInstr &&
"Lost some non-NOP instructions during scheduling!");
@@ -643,12 +643,12 @@
// First find the dummy instructions at the start of the basic block
MachineBasicBlock::iterator I = MBB.begin();
for ( ; I != MBB.end(); ++I)
- if (! mii.isDummyPhiInstr((*I)->getOpcode()))
+ if (! mii.isDummyPhiInstr(I->getOpcode()))
break;
- // Erase all except the dummy PHI instructions from MBB, and
+ // Remove all except the dummy PHI instructions from MBB, and
// pre-allocate create space for the ones we will put back in.
- MBB.erase(I, MBB.end());
+ while (I != MBB.end()) MBB.remove(I);
InstrSchedule::const_iterator NIend = S.isched.end();
for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
@@ -1175,25 +1175,25 @@
//
unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
MachineBasicBlock& MBB = node->getMachineBasicBlock();
- assert(MBB[firstDelaySlotIdx - 1] == brInstr &&
+ assert(&MBB[firstDelaySlotIdx - 1] == brInstr &&
"Incorrect instr. index in basic block for brInstr");
// First find all useful instructions already in the delay slots
// and USE THEM. We'll throw away the unused alternatives below
//
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (! mii.isNop(MBB[i]->getOpcode()))
+ if (! mii.isNop(MBB[i].getOpcode()))
sdelayNodeVec.insert(sdelayNodeVec.begin(),
- graph->getGraphNodeForInstr(MBB[i]));
+ graph->getGraphNodeForInstr(&MBB[i]));
// Then find the NOPs and keep only as many as are needed.
// Put the rest in nopNodeVec to be deleted.
for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx + ndelays; ++i)
- if (mii.isNop(MBB[i]->getOpcode()))
+ if (mii.isNop(MBB[i].getOpcode()))
if (sdelayNodeVec.size() < ndelays)
- sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ sdelayNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
else {
- nopNodeVec.push_back(graph->getGraphNodeForInstr(MBB[i]));
+ nopNodeVec.push_back(graph->getGraphNodeForInstr(&MBB[i]));
//remove the MI from the Machine Code For Instruction
const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
@@ -1202,7 +1202,7 @@
for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
- if (*mciI==MBB[i])
+ if (*mciI == &MBB[i])
llvmMvec.erase(mciI);
}
}
@@ -1282,10 +1282,10 @@
//
delayNodeVec.clear();
for (unsigned i=0; i < MBB.size(); ++i)
- if (MBB[i] != brInstr &&
- mii.getNumDelaySlots(MBB[i]->getOpcode()) > 0)
+ if (&MBB[i] != brInstr &&
+ mii.getNumDelaySlots(MBB[i].getOpcode()) > 0)
{
- SchedGraphNode* node = graph->getGraphNodeForInstr(MBB[i]);
+ SchedGraphNode* node = graph->getGraphNodeForInstr(&MBB[i]);
ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
}
}
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