[llvm-commits] CVS: llvm/lib/Target/Sparc/EmitAssembly.cpp PeepholeOpts.cpp PrologEpilogCodeInserter.cpp SparcInstrSelection.cpp SparcRegInfo.cpp
Brian Gaeke
gaeke at cs.uiuc.edu
Wed Feb 11 14:48:19 PST 2004
Changes in directory llvm/lib/Target/Sparc:
EmitAssembly.cpp updated: 1.103 -> 1.104
PeepholeOpts.cpp updated: 1.17 -> 1.18
PrologEpilogCodeInserter.cpp updated: 1.32 -> 1.33
SparcInstrSelection.cpp updated: 1.130 -> 1.131
SparcRegInfo.cpp updated: 1.116 -> 1.117
---
Log message:
MachineInstr::getOpCode() --> getOpcode() in SPARC back-end.
---
Diffs of the changes: (+18 -18)
Index: llvm/lib/Target/Sparc/EmitAssembly.cpp
diff -u llvm/lib/Target/Sparc/EmitAssembly.cpp:1.103 llvm/lib/Target/Sparc/EmitAssembly.cpp:1.104
--- llvm/lib/Target/Sparc/EmitAssembly.cpp:1.103 Mon Feb 9 23:16:44 2004
+++ llvm/lib/Target/Sparc/EmitAssembly.cpp Wed Feb 11 14:47:31 2004
@@ -566,7 +566,7 @@
inline bool
SparcAsmPrinter::OpIsBranchTargetLabel(const MachineInstr *MI,
unsigned int opNum) {
- switch (MI->getOpCode()) {
+ switch (MI->getOpcode()) {
case V9::JMPLCALLr:
case V9::JMPLCALLi:
case V9::JMPLRETr:
@@ -580,9 +580,9 @@
inline bool
SparcAsmPrinter::OpIsMemoryAddressBase(const MachineInstr *MI,
unsigned int opNum) {
- if (Target.getInstrInfo().isLoad(MI->getOpCode()))
+ if (Target.getInstrInfo().isLoad(MI->getOpcode()))
return (opNum == 0);
- else if (Target.getInstrInfo().isStore(MI->getOpCode()))
+ else if (Target.getInstrInfo().isStore(MI->getOpcode()))
return (opNum == 1);
else
return false;
@@ -601,15 +601,15 @@
const MachineOperand& mop = MI->getOperand(opNum);
if (OpIsBranchTargetLabel(MI, opNum)) {
- PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
+ PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode());
return 2;
} else if (OpIsMemoryAddressBase(MI, opNum)) {
toAsm << "[";
- PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpCode());
+ PrintOp1PlusOp2(mop, MI->getOperand(opNum+1), MI->getOpcode());
toAsm << "]";
return 2;
} else {
- printOneOperand(mop, MI->getOpCode());
+ printOneOperand(mop, MI->getOpcode());
return 1;
}
}
@@ -691,7 +691,7 @@
}
void SparcAsmPrinter::emitMachineInst(const MachineInstr *MI) {
- unsigned Opcode = MI->getOpCode();
+ unsigned Opcode = MI->getOpcode();
if (Target.getInstrInfo().isDummyPhiInstr(Opcode))
return; // IGNORE PHI NODES
Index: llvm/lib/Target/Sparc/PeepholeOpts.cpp
diff -u llvm/lib/Target/Sparc/PeepholeOpts.cpp:1.17 llvm/lib/Target/Sparc/PeepholeOpts.cpp:1.18
--- llvm/lib/Target/Sparc/PeepholeOpts.cpp:1.17 Wed Dec 17 16:08:20 2003
+++ llvm/lib/Target/Sparc/PeepholeOpts.cpp Wed Feb 11 14:47:32 2004
@@ -32,7 +32,7 @@
if (BBI != mvec.begin()) {
const TargetInstrInfo& mii = target.getInstrInfo();
MachineInstr* predMI = *(BBI-1);
- if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpCode())) {
+ if (unsigned ndelay = mii.getNumDelaySlots(predMI->getOpcode())) {
// This instruction is in a delay slot of its predecessor, so
// replace it with a nop. By replacing in place, we save having
// to update the I-I maps.
@@ -61,12 +61,12 @@
//----------------------------------------------------------------------------
static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
- if (MI->getOpCode() == V9::FMOVS || MI->getOpCode() == V9::FMOVD) {
+ if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
return (// both operands are allocated to the same register
MI->getOperand(0).getAllocatedRegNum() ==
MI->getOperand(1).getAllocatedRegNum());
- } else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr ||
- MI->getOpCode() == V9::ADDi || MI->getOpCode() == V9::ORi) {
+ } else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
+ MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
unsigned srcWithDestReg;
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
Index: llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp
diff -u llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.32 llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.33
--- llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp:1.32 Wed Nov 12 18:18:04 2003
+++ llvm/lib/Target/Sparc/PrologEpilogCodeInserter.cpp Wed Feb 11 14:47:32 2004
@@ -155,7 +155,7 @@
// Remove the NOPs in the delay slots of the return instruction
unsigned numNOPs = 0;
- while (termMvec.back()->getOpCode() == V9::NOP)
+ while (termMvec.back()->getOpcode() == V9::NOP)
{
assert( termMvec.back() == MBB.back());
delete MBB.pop_back();
@@ -166,7 +166,7 @@
// Check that we found the right number of NOPs and have the right
// number of instructions to replace them.
- unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpCode());
+ unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
Index: llvm/lib/Target/Sparc/SparcInstrSelection.cpp
diff -u llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.130 llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.131
--- llvm/lib/Target/Sparc/SparcInstrSelection.cpp:1.130 Mon Jan 12 12:08:18 2004
+++ llvm/lib/Target/Sparc/SparcInstrSelection.cpp Wed Feb 11 14:47:32 2004
@@ -874,7 +874,7 @@
if (firstNewInstr < mvec.size()) {
cost = 0;
for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
- cost += target.getInstrInfo().minLatency(mvec[i]->getOpCode());
+ cost += target.getInstrInfo().minLatency(mvec[i]->getOpcode());
}
return cost;
@@ -1918,7 +1918,7 @@
const MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(
cast<InstructionNode>(subtreeRoot->parent())->getInstruction());
- if (mcfi.size() == 0 || mcfi.front()->getOpCode() == V9::FSMULD)
+ if (mcfi.size() == 0 || mcfi.front()->getOpcode() == V9::FSMULD)
forwardOperandNum = 0; // forward first operand to user
}
Index: llvm/lib/Target/Sparc/SparcRegInfo.cpp
diff -u llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.116 llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.117
--- llvm/lib/Target/Sparc/SparcRegInfo.cpp:1.116 Fri Jan 9 10:17:09 2004
+++ llvm/lib/Target/Sparc/SparcRegInfo.cpp Wed Feb 11 14:47:33 2004
@@ -312,7 +312,7 @@
void SparcRegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert(target.getInstrInfo().isReturn(RetMI->getOpCode()));
+ assert(target.getInstrInfo().isReturn(RetMI->getOpcode()));
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
@@ -570,7 +570,7 @@
//---------------------------------------------------------------------------
void SparcRegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
- assert ( (target.getInstrInfo()).isCall(CallMI->getOpCode()) );
+ assert ( (target.getInstrInfo()).isCall(CallMI->getOpcode()) );
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
@@ -639,7 +639,7 @@
void SparcRegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
- assert( (target.getInstrInfo()).isReturn( RetMI->getOpCode() ) );
+ assert( (target.getInstrInfo()).isReturn( RetMI->getOpcode() ) );
suggestReg4RetAddr(RetMI, LRI);
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